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synth_xilinx to use _ABC macro, and perform muxpack again

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This commit is contained in:
Eddie Hung 2019-06-21 15:48:20 -07:00
parent 9abde12110
commit aa0b107afb
1 changed files with 5 additions and 5 deletions
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10
techlibs/xilinx/synth_xilinx.cc
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@ -206,9 +206,9 @@ struct SynthXilinxPass : public ScriptPass
{ {
if (check_label("begin")) { if (check_label("begin")) {
if (vpr) if (vpr)
run("read_verilog -lib -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); run("read_verilog -lib -icells -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
else else
run("read_verilog -lib -D _ABC +/xilinx/cells_sim.v"); run("read_verilog -lib -icells -D _ABC +/xilinx/cells_sim.v");
run("read_verilog -lib +/xilinx/cells_xtra.v"); run("read_verilog -lib +/xilinx/cells_xtra.v");
@ -238,8 +238,8 @@ struct SynthXilinxPass : public ScriptPass
run("memory -nomap"); run("memory -nomap");
run("opt_clean"); run("opt_clean");
//if (!nomux || help_mode) if (!nomux || help_mode)
// run("muxpack", "(skip if '-nomux')"); run("muxpack", " (skip if '-nomux')");
// shregmap -tech xilinx can cope with $shiftx and $mux // shregmap -tech xilinx can cope with $shiftx and $mux
// cells for identifying variable-length shift registers, // cells for identifying variable-length shift registers,
@ -308,7 +308,7 @@ struct SynthXilinxPass : public ScriptPass
} }
if (check_label("map_cells")) { if (check_label("map_cells")) {
run("techmap -map +/techmap.v -map +/xilinx/cells_map.v"); run("techmap -map +/techmap.v -D _ABC -map +/xilinx/cells_map.v");
run("clean"); run("clean");
} }