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xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.

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Marcin Kościelnicki 2019-07-11 21:13:12 +02:00
parent 9112850800
commit a9efacd01d
2 changed files with 6 additions and 6 deletions
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4
techlibs/xilinx/cells_sim.v
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@ -226,7 +226,7 @@ module FDRE (output reg Q, input C, CE, D, R);
endmodule
module FDSE (output reg Q, input C, CE, D, S);
parameter [0:0] INIT = 1'b0;
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_S_INVERTED = 1'b0;
@ -252,7 +252,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
endmodule
module FDPE (output reg Q, input C, CE, D, PRE);
parameter [0:0] INIT = 1'b0;
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;