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kernel: add design -delete option

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This commit is contained in:
Eddie Hung 2020-04-14 10:33:55 -07:00
parent 90a1c6b6a4
commit a9ec0defb9
2 changed files with 22 additions and 1 deletions
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1
CHANGELOG
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@ -64,6 +64,7 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added "opt_lut_ins" pass
- Added "logger" pass
- Removed "dffsr2dff" (use opt_rmdff instead)
- Added "design -delete"
Yosys 0.8 .. Yosys 0.9
----------------------

22
passes/cmds/design.cc
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@ -99,6 +99,11 @@ struct DesignPass : public Pass {
log("The Verilog front-end remembers defined macros and top-level declarations\n");
log("between calls to 'read_verilog'. This command resets this memory.\n");
log("\n");
log(" design -delete <name>\n");
log("\n");
log("Delete the design previously saved under the given name.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
@ -110,7 +115,7 @@ struct DesignPass : public Pass {
bool pop_mode = false;
bool import_mode = false;
RTLIL::Design *copy_from_design = NULL, *copy_to_design = NULL;
std::string save_name, load_name, as_name;
std::string save_name, load_name, as_name, delete_name;
std::vector<RTLIL::Module*> copy_src_modules;
size_t argidx;
@ -190,6 +195,13 @@ struct DesignPass : public Pass {
as_name = args[++argidx];
continue;
}
if (!got_mode && args[argidx] == "-delete" && argidx+1 < args.size()) {
got_mode = true;
delete_name = args[++argidx];
if (saved_designs.count(delete_name) == 0)
log_cmd_error("No saved design '%s' found!\n", delete_name.c_str());
continue;
}
break;
}
@ -379,6 +391,14 @@ struct DesignPass : public Pass {
pushed_designs.pop_back();
}
}
if (!delete_name.empty())
{
auto it = saved_designs.find(delete_name);
log_assert(it != saved_designs.end());
delete it->second;
saved_designs.erase(it);
}
}
} DesignPass;