Merge from upstream

tests/verific/mixed_flist.flist

@@ -0,0 +1,2 @@
+mixed_flist.sv
+mixed_flist.vhd

tests/verific/mixed_flist.sv

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+module sv_top(input logic a, output logic y);
+	// Instantiates VHDL entity to ensure mixed -f list is required
+	vhdl_mod u_vhdl(.a(a), .y(y));
+endmodule

tests/verific/mixed_flist.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity vhdl_mod is
+	port (
+		a : in std_logic;
+		y : out std_logic
+	);
+end entity vhdl_mod;
+
+architecture rtl of vhdl_mod is
+begin
+	y <= a;
+end architecture rtl;

tests/verific/mixed_flist.ys

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+verific -f -sv mixed_flist.flist
+verific -import sv_top
+select -assert-mod-count 1 sv_top