mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-30 12:25:52 +00:00
Code Activity

Revert Verific flags

Browse source
This commit is contained in:
Akash Levy 2024-05-25 23:21:31 -07:00
parent f0c4aa7059
commit a98fcbd48b
1 changed files with 2 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

4
frontends/verific/verific.cc
View file

@ -3209,8 +3209,8 @@ struct VerificPass : public Pass {
RuntimeFlags::SetVar("db_change_inplace_ram_blocking_write_before_read", 1);
RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
RuntimeFlags::SetVar("veri_extract_multiport_rams", 0);
RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 0);
RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1);
#ifdef VERIFIC_VHDL_SUPPORT
RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);