Merge branch 'YosysHQ:main' into main

tests/verilog/.gitignore

@@ -1,6 +1,7 @@
 /const_arst.v
 /const_sr.v
 /doubleslash.v
+/reset_auto_counter.v
 /roundtrip_proc_1.v
 /roundtrip_proc_2.v
 /assign_to_reg.v

tests/verilog/reset_auto_counter.ys

@@ -0,0 +1,17 @@
+read_verilog -sv <<EOT
+module arithmetic (
+    input  logic [7:0] _0_,
+    input  logic [7:0] _1_,
+    output logic [7:0] _2_,
+);
+  assign _2_ = _0_ + _1_;
+
+endmodule : arithmetic
+EOT
+
+hierarchy
+techmap
+write_verilog reset_auto_counter.v
+! ! grep -qE '_0+0_' reset_auto_counter.v
+! ! grep -qE '_0+1_' reset_auto_counter.v
+! ! grep -qE '_0+2_' reset_auto_counter.v