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Deprecate RTLIL::id2cstr()

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This commit is contained in:
Robert O'Callahan 2025-09-16 23:40:35 +00:00
parent b95549b469
commit a8ff020829
21 changed files with 75 additions and 78 deletions
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18
passes/sat/expose.cc
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@ -471,7 +471,7 @@ struct ExposePass : public Pass {
{
if (!w->port_input) {
w->port_input = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
log("New module port: %s/%s\n", log_id(module->name), log_id(w->name));
wire_map[w] = NEW_ID;
}
}
@ -479,7 +479,7 @@ struct ExposePass : public Pass {
{
if (!w->port_output) {
w->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
log("New module port: %s/%s\n", log_id(module->name), log_id(w->name));
}
if (flag_cut) {
@ -555,7 +555,7 @@ struct ExposePass : public Pass {
RTLIL::Wire *wire_q = add_new_wire(module, wire->name.str() + sep + "q", wire->width);
wire_q->port_input = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_q->name));
log("New module port: %s/%s\n", log_id(module->name), log_id(wire_q->name));
RTLIL::SigSig connect_q;
for (size_t i = 0; i < wire_bits_vec.size(); i++) {
@ -569,12 +569,12 @@ struct ExposePass : public Pass {
RTLIL::Wire *wire_d = add_new_wire(module, wire->name.str() + sep + "d", wire->width);
wire_d->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_d->name));
log("New module port: %s/%s\n", log_id(module->name), log_id(wire_d->name));
module->connect(RTLIL::SigSig(wire_d, info.sig_d));
RTLIL::Wire *wire_c = add_new_wire(module, wire->name.str() + sep + "c");
wire_c->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_c->name));
log("New module port: %s/%s\n", log_id(module->name), log_id(wire_c->name));
if (info.clk_polarity) {
module->connect(RTLIL::SigSig(wire_c, info.sig_clk));
} else {
@ -590,7 +590,7 @@ struct ExposePass : public Pass {
{
RTLIL::Wire *wire_r = add_new_wire(module, wire->name.str() + sep + "r");
wire_r->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_r->name));
log("New module port: %s/%s\n", log_id(module->name), log_id(wire_r->name));
if (info.arst_polarity) {
module->connect(RTLIL::SigSig(wire_r, info.sig_arst));
} else {
@ -604,7 +604,7 @@ struct ExposePass : public Pass {
RTLIL::Wire *wire_v = add_new_wire(module, wire->name.str() + sep + "v", wire->width);
wire_v->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_v->name));
log("New module port: %s/%s\n", log_id(module->name), log_id(wire_v->name));
module->connect(RTLIL::SigSig(wire_v, info.arst_value));
}
}
@ -638,7 +638,7 @@ struct ExposePass : public Pass {
if (p->port_output)
w->port_input = true;
log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
log("New module port: %s/%s (%s)\n", log_id(module->name), log_id(w->name), log_id(cell->type));
RTLIL::SigSpec sig;
if (cell->hasPort(p->name))
@ -660,7 +660,7 @@ struct ExposePass : public Pass {
if (ct.cell_output(cell->type, it.first))
w->port_input = true;
log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
log("New module port: %s/%s (%s)\n", log_id(module->name), log_id(w->name), log_id(cell->type));
if (w->port_input)
module->connect(RTLIL::SigSig(it.second, w));