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Deprecate RTLIL::id2cstr()

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This commit is contained in:
Robert O'Callahan 2025-09-16 23:40:35 +00:00
parent b95549b469
commit a8ff020829
21 changed files with 75 additions and 78 deletions
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18
passes/sat/expose.cc
View file

@ -471,7 +471,7 @@ struct ExposePass : public Pass {
{
if (!w->port_input) {
w->port_input = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
log("New module port: %s/%s\n", log_id(module->name), log_id(w->name));
wire_map[w] = NEW_ID;
}
}
@ -479,7 +479,7 @@ struct ExposePass : public Pass {
{
if (!w->port_output) {
w->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
log("New module port: %s/%s\n", log_id(module->name), log_id(w->name));
}
if (flag_cut) {
@ -555,7 +555,7 @@ struct ExposePass : public Pass {
RTLIL::Wire *wire_q = add_new_wire(module, wire->name.str() + sep + "q", wire->width);
wire_q->port_input = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_q->name));
log("New module port: %s/%s\n", log_id(module->name), log_id(wire_q->name));
RTLIL::SigSig connect_q;
for (size_t i = 0; i < wire_bits_vec.size(); i++) {
@ -569,12 +569,12 @@ struct ExposePass : public Pass {
RTLIL::Wire *wire_d = add_new_wire(module, wire->name.str() + sep + "d", wire->width);
wire_d->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_d->name));
log("New module port: %s/%s\n", log_id(module->name), log_id(wire_d->name));
module->connect(RTLIL::SigSig(wire_d, info.sig_d));
RTLIL::Wire *wire_c = add_new_wire(module, wire->name.str() + sep + "c");
wire_c->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_c->name));
log("New module port: %s/%s\n", log_id(module->name), log_id(wire_c->name));
if (info.clk_polarity) {
module->connect(RTLIL::SigSig(wire_c, info.sig_clk));
} else {
@ -590,7 +590,7 @@ struct ExposePass : public Pass {
{
RTLIL::Wire *wire_r = add_new_wire(module, wire->name.str() + sep + "r");
wire_r->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_r->name));
log("New module port: %s/%s\n", log_id(module->name), log_id(wire_r->name));
if (info.arst_polarity) {
module->connect(RTLIL::SigSig(wire_r, info.sig_arst));
} else {
@ -604,7 +604,7 @@ struct ExposePass : public Pass {
RTLIL::Wire *wire_v = add_new_wire(module, wire->name.str() + sep + "v", wire->width);
wire_v->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_v->name));
log("New module port: %s/%s\n", log_id(module->name), log_id(wire_v->name));
module->connect(RTLIL::SigSig(wire_v, info.arst_value));
}
}
@ -638,7 +638,7 @@ struct ExposePass : public Pass {
if (p->port_output)
w->port_input = true;
log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
log("New module port: %s/%s (%s)\n", log_id(module->name), log_id(w->name), log_id(cell->type));
RTLIL::SigSpec sig;
if (cell->hasPort(p->name))
@ -660,7 +660,7 @@ struct ExposePass : public Pass {
if (ct.cell_output(cell->type, it.first))
w->port_input = true;
log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
log("New module port: %s/%s (%s)\n", log_id(module->name), log_id(w->name), log_id(cell->type));
if (w->port_input)
module->connect(RTLIL::SigSig(it.second, w));

10
passes/sat/freduce.cc
View file

@ -139,7 +139,7 @@ struct FindReducedInputs
if (ez_cells.count(drv.first) == 0) {
satgen.setContext(&sigmap, "A");
if (!satgen.importCell(drv.first))
log_error("Can't create SAT model for cell %s (%s)!\n", RTLIL::id2cstr(drv.first->name), RTLIL::id2cstr(drv.first->type));
log_error("Can't create SAT model for cell %s (%s)!\n", log_id(drv.first->name), log_id(drv.first->type));
satgen.setContext(&sigmap, "B");
if (!satgen.importCell(drv.first))
log_abort();
@ -256,7 +256,7 @@ struct PerformReduction
std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> &drv = drivers.at(out);
if (celldone.count(drv.first) == 0) {
if (!satgen.importCell(drv.first))
log_error("Can't create SAT model for cell %s (%s)!\n", RTLIL::id2cstr(drv.first->name), RTLIL::id2cstr(drv.first->type));
log_error("Can't create SAT model for cell %s (%s)!\n", log_id(drv.first->name), log_id(drv.first->type));
celldone.insert(drv.first);
}
int max_child_depth = 0;
@ -595,14 +595,14 @@ struct FreduceWorker
void dump()
{
std::string filename = stringf("%s_%s_%05d.il", dump_prefix, RTLIL::id2cstr(module->name), reduce_counter);
std::string filename = stringf("%s_%s_%05d.il", dump_prefix, log_id(module->name), reduce_counter);
log("%s Writing dump file `%s'.\n", reduce_counter ? " " : "", filename);
Pass::call(design, stringf("dump -outfile %s %s", filename, design->selected_active_module.empty() ? module->name.c_str() : ""));
}
int run()
{
log("Running functional reduction on module %s:\n", RTLIL::id2cstr(module->name));
log("Running functional reduction on module %s:\n", log_id(module->name));
CellTypes ct;
ct.setup_internals();
@ -749,7 +749,7 @@ struct FreduceWorker
}
}
log(" Rewired a total of %d signal bits in module %s.\n", rewired_sigbits, RTLIL::id2cstr(module->name));
log(" Rewired a total of %d signal bits in module %s.\n", rewired_sigbits, log_id(module->name));
return rewired_sigbits;
}
};

2
passes/sat/miter.cc
View file

@ -128,7 +128,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
log_cmd_error("No matching port in gold module was found for %s!\n", gate_wire->name.c_str());
}
log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::id2cstr(miter_name), RTLIL::id2cstr(gold_name), RTLIL::id2cstr(gate_name));
log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", log_id(miter_name), log_id(gold_name), log_id(gate_name));
RTLIL::Module *miter_module = new RTLIL::Module;
miter_module->name = miter_name;

6
passes/sat/sat.cc
View file

@ -227,16 +227,16 @@ struct SatHelper
int import_cell_counter = 0;
for (auto cell : module->cells())
if (design->selected(module, cell)) {
// log("Import cell: %s\n", RTLIL::id2cstr(cell->name));
// log("Import cell: %s\n", log_id(cell->name));
if (satgen.importCell(cell, timestep)) {
for (auto &p : cell->connections())
if (ct.cell_output(cell->type, p.first))
show_drivers.insert(sigmap(p.second), cell);
import_cell_counter++;
} else if (ignore_unknown_cells)
log_warning("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
log_warning("Failed to import cell %s (type %s) to SAT database.\n", log_id(cell->name), log_id(cell->type));
else
log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
log_error("Failed to import cell %s (type %s) to SAT database.\n", log_id(cell->name), log_id(cell->type));
}
log("Imported %d cells to SAT database.\n", import_cell_counter);