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Deprecate RTLIL::id2cstr()

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This commit is contained in:
Robert O'Callahan 2025-09-16 23:40:35 +00:00
parent b95549b469
commit a8ff020829
21 changed files with 75 additions and 78 deletions
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14
docs/source/code_examples/functional/dummy.cc
View file

@ -24,19 +24,19 @@ struct FunctionalDummyBackend : public Backend {
// write node functions
for (auto node : ir)
*f << " assign " << id2cstr(node.name())
*f << " assign " << log_id(node.name())
<< " = " << node.to_string() << "\n";
*f << "\n";
// write outputs and next state
for (auto output : ir.outputs())
*f << " " << id2cstr(output->kind)
<< " " << id2cstr(output->name)
<< " = " << id2cstr(output->value().name()) << "\n";
*f << " " << log_id(output->kind)
<< " " << log_id(output->name)
<< " = " << log_id(output->value().name()) << "\n";
for (auto state : ir.states())
*f << " " << id2cstr(state->kind)
<< " " << id2cstr(state->name)
<< " = " << id2cstr(state->next_value().name()) << "\n";
*f << " " << log_id(state->kind)
<< " " << log_id(state->name)
<< " = " << log_id(state->next_value().name()) << "\n";
}
}
} FunctionalDummyBackend;

6
docs/source/code_examples/stubnets/stubnets.cc
View file

@ -27,7 +27,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
// count output lines for this module (needed only for summary output at the end)
int line_count = 0;
log("Looking for stub wires in module %s:\n", RTLIL::id2cstr(module->name));
log("Looking for stub wires in module %s:\n", log_id(module->name));
// For all ports on all cells
for (auto &cell_iter : module->cells_)
@ -74,11 +74,11 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
// report stub bits and/or stub wires, don't report single bits
// if called with report_bits set to false.
if (GetSize(stub_bits) == GetSize(sig)) {
log(" found stub wire: %s\n", RTLIL::id2cstr(wire->name));
log(" found stub wire: %s\n", log_id(wire->name));
} else {
if (!report_bits)
continue;
log(" found wire with stub bits: %s [", RTLIL::id2cstr(wire->name));
log(" found wire with stub bits: %s [", log_id(wire->name));
for (int bit : stub_bits)
log("%s%d", bit == *stub_bits.begin() ? "" : ", ", bit);
log("]\n");

2
docs/source/yosys_internals/extending_yosys/extensions.rst
View file

@ -231,7 +231,7 @@ Use ``log_error()`` to report a non-recoverable error:
if (design->modules.count(module->name) != 0)
log_error("A module with the name %s already exists!\n",
RTLIL::id2cstr(module->name));
log_id(module->name));
Use ``log_cmd_error()`` to report a recoverable error:

2
docs/source/yosys_internals/extending_yosys/functional_ir.rst
View file

@ -181,7 +181,7 @@ pointer ``f`` to the output file, or stdout if none is given.
For this minimal example all we are doing is printing out each node. The
``node.name()`` method returns an ``RTLIL::IdString``, which we convert for
printing with ``id2cstr()``. Then, to print the function of the node, we use
printing with ``log_id()``. Then, to print the function of the node, we use
``node.to_string()`` which gives us a string of the form ``function(args)``. The
``function`` part is the result of ``Functional::IR::fn_to_string(node.fn())``;
while ``args`` is the zero or more arguments passed to the function, most