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Creating $meminit cells in verilog front-end

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Clifford Wolf 2015-02-14 10:49:30 +01:00
parent 910556560f
commit a8e9d37c14
4 changed files with 57 additions and 33 deletions
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frontends/ast/ast.h
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@ -107,6 +107,7 @@ namespace AST
AST_TERNARY,
AST_MEMRD,
AST_MEMWR,
AST_MEMINIT,
AST_TCALL,
AST_ASSIGN,
@ -299,7 +300,7 @@ namespace AST_INTERNAL
extern std::map<std::string, AST::AstNode*> current_scope;
extern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr;
extern RTLIL::SigSpec ignoreThisSignalsInInitial;
extern AST::AstNode *current_top_block, *current_block, *current_block_child;
extern AST::AstNode *current_always, *current_top_block, *current_block, *current_block_child;
extern AST::AstModule *current_module;
struct ProcessGenerator;
}