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Creating $meminit cells in verilog front-end

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This commit is contained in:
Clifford Wolf 2015-02-14 10:49:30 +01:00
parent 910556560f
commit a8e9d37c14
4 changed files with 57 additions and 33 deletions
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frontends/ast/ast.cc
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@ -58,7 +58,7 @@ namespace AST_INTERNAL {
std::map<std::string, AstNode*> current_scope;
const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr = NULL;
RTLIL::SigSpec ignoreThisSignalsInInitial;
AstNode *current_top_block, *current_block, *current_block_child;
AstNode *current_always, *current_top_block, *current_block, *current_block_child;
AstModule *current_module;
}
@ -132,6 +132,7 @@ std::string AST::type2str(AstNodeType type)
X(AST_TERNARY)
X(AST_MEMRD)
X(AST_MEMWR)
X(AST_MEMINIT)
X(AST_TCALL)
X(AST_ASSIGN)
X(AST_CELL)