mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-23 07:32:32 +00:00
Code Activity

Removed simulation and isValidGatingSignal function

Browse source
This commit is contained in:
AdvaySingh1 2026-02-17 14:07:22 -08:00
parent fa9e7a77d7
commit a8e4fccc56
3 changed files with 42 additions and 157 deletions
Download patch file Download diff file Expand all files Collapse all files

12
passes/techmap/clockgate.cc
View file

@ -328,6 +328,8 @@ struct ClockgatePass : public Pass {
pool<Cell*> ce_ffs;
dict<ClkNetInfo, GClkNetInfo> clk_nets;
log("Found %zu CE FFs\n", ce_ffs.size());
int gated_flop_count = 0;
for (auto module : design->selected_unboxed_whole_modules()) {
for (auto cell : module->cells()) {
@ -337,11 +339,14 @@ struct ClockgatePass : public Pass {
FfData ff(nullptr, cell);
// It would be odd to get constants, but we better handle it
if (ff.has_ce) {
log("FF %s has CE\n", cell->name);
if (!ff.sig_clk.is_bit() || !ff.sig_ce.is_bit())
continue;
if (!ff.sig_clk[0].is_wire() || !ff.sig_ce[0].is_wire())
continue;
log("FF %s has valid CE and CLK\n", cell->name);
ce_ffs.insert(cell);
ClkNetInfo info = clk_info_from_ff(ff);
@ -352,6 +357,8 @@ struct ClockgatePass : public Pass {
}
}
log("Found %zu clk_nets\n", clk_nets.size());
for (auto& clk_net : clk_nets) {
auto& clk = clk_net.first;
auto& gclk = clk_net.second;
@ -385,15 +392,20 @@ struct ClockgatePass : public Pass {
}
}
log("Found %zu clk_nets\n", clk_nets.size());
for (auto cell : ce_ffs) {
FfData ff(nullptr, cell);
ClkNetInfo info = clk_info_from_ff(ff);
auto it = clk_nets.find(info);
log_assert(it != clk_nets.end() && "Bug: desync ce_ffs and clk_nets");
log("Found new_net for %s\n", cell->name);
if (!it->second.new_net)
continue;
log("Tryuing to fix up FF %s\n", cell->name);
log_debug("Fix up FF %s\n", cell->name);
// Now we start messing with the design
ff.has_ce = false;