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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3

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Clifford Wolf 2014-07-23 08:40:31 +02:00
parent 260c19ec5a
commit a8d3a68971
15 changed files with 33 additions and 47 deletions
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2
passes/sat/miter.cc
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@ -174,7 +174,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
eqx_cell->parameters["\\Y_WIDTH"] = 1;
eqx_cell->parameters["\\A_SIGNED"] = 0;
eqx_cell->parameters["\\B_SIGNED"] = 0;
eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, 1, i);
eqx_cell->connections["\\A"] = RTLIL::SigSpec::grml(w2_gold, i);
eqx_cell->connections["\\B"] = RTLIL::State::Sx;
eqx_cell->connections["\\Y"] = gold_x.extract(i, 1);
miter_module->add(eqx_cell);