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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3

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This commit is contained in:
Clifford Wolf 2014-07-23 08:40:31 +02:00
parent 260c19ec5a
commit a8d3a68971
15 changed files with 33 additions and 47 deletions
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4
passes/sat/eval.cc
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@ -260,8 +260,8 @@ struct VlogHammerReporter
for (int i = 0; i < int(inputs.size()); i++) {
RTLIL::Wire *wire = module->wires.at(inputs[i]);
for (int j = input_widths[i]-1; j >= 0; j--) {
ce.set(RTLIL::SigSpec(wire, 1, j), bits.back());
recorded_set_vars.append(RTLIL::SigSpec(wire, 1, j));
ce.set(RTLIL::SigSpec::grml(wire, j), bits.back());
recorded_set_vars.append(RTLIL::SigSpec::grml(wire, j));
recorded_set_vals.bits.push_back(bits.back());
bits.pop_back();
}

2
passes/sat/miter.cc
View file

@ -174,7 +174,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
eqx_cell->parameters["\\Y_WIDTH"] = 1;
eqx_cell->parameters["\\A_SIGNED"] = 0;
eqx_cell->parameters["\\B_SIGNED"] = 0;
eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, 1, i);
eqx_cell->connections["\\A"] = RTLIL::SigSpec::grml(w2_gold, i);
eqx_cell->connections["\\B"] = RTLIL::State::Sx;
eqx_cell->connections["\\Y"] = gold_x.extract(i, 1);
miter_module->add(eqx_cell);

10
passes/sat/share.cc
View file

@ -292,8 +292,8 @@ struct ShareWorker
supercell->connections["\\Y"] = y;
module->add(supercell);
RTLIL::SigSpec new_y1(y, y1.size(), 0);
RTLIL::SigSpec new_y2(y, y2.size(), 0);
RTLIL::SigSpec new_y1 = RTLIL::SigSpec::grml(y, 0, y1.size());
RTLIL::SigSpec new_y2 = RTLIL::SigSpec::grml(y, 0, y2.size());
module->connections.push_back(RTLIL::SigSig(y1, new_y1));
module->connections.push_back(RTLIL::SigSig(y2, new_y2));
@ -405,8 +405,8 @@ struct ShareWorker
supercell->connections["\\Y"] = y;
supercell->check();
RTLIL::SigSpec new_y1(y, y1.size(), 0);
RTLIL::SigSpec new_y2(y, y2.size(), 0);
RTLIL::SigSpec new_y1 = RTLIL::SigSpec::grml(y, 0, y1.size());
RTLIL::SigSpec new_y2 = RTLIL::SigSpec::grml(y, 0, y2.size());
module->connections.push_back(RTLIL::SigSig(y1, new_y1));
module->connections.push_back(RTLIL::SigSig(y2, new_y2));
@ -620,7 +620,7 @@ struct ShareWorker
RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0);
for (auto &p : activation_patterns) {
all_cases_wire->width++;
module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, 1, all_cases_wire->width - 1));
module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec::grml(all_cases_wire, all_cases_wire->width - 1));
}
if (all_cases_wire->width == 1)
return all_cases_wire;