mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 17:15:33 +00:00
Code Activity

Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3

Browse source
This commit is contained in:
Clifford Wolf 2014-07-23 08:40:31 +02:00
parent 260c19ec5a
commit a8d3a68971
15 changed files with 33 additions and 47 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/abc/abc.cc
View file

@ -466,7 +466,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
clk_str = clk_str.substr(1);
}
if (module->wires.count(RTLIL::escape_id(clk_str)) != 0)
clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 1, 0));
clk_sig = assign_map(RTLIL::SigSpec::grml(module->wires.at(RTLIL::escape_id(clk_str)), 0));
}
if (dff_mode && clk_sig.size() == 0)

16
passes/fsm/fsm_map.cc
View file

@ -30,7 +30,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
RTLIL::SigSpec cases_vector;
for (int in_state : fullstate_cache)
cases_vector.append(RTLIL::SigSpec(state_onehot, 1, in_state));
cases_vector.append(RTLIL::SigSpec::grml(state_onehot, in_state));
for (auto &it : pattern_cache)
{
@ -47,7 +47,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
for (int in_state : it.second)
if (fullstate_cache.count(in_state) == 0)
or_sig.append(RTLIL::SigSpec(state_onehot, 1, in_state));
or_sig.append(RTLIL::SigSpec::grml(state_onehot, in_state));
or_sig.optimize();
if (or_sig.size() == 0)
@ -215,7 +215,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
for (size_t j = 0; j < state.bits.size(); j++)
if (state.bits[j] == RTLIL::State::S0 || state.bits[j] == RTLIL::State::S1) {
sig_a.append(RTLIL::SigSpec(state_wire, 1, j));
sig_a.append(RTLIL::SigSpec::grml(state_wire, j));
sig_b.append(RTLIL::SigSpec(state.bits[j]));
}
sig_a.optimize();
@ -223,7 +223,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
if (sig_b == RTLIL::SigSpec(RTLIL::State::S1))
{
module->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(state_onehot, 1, i), sig_a));
module->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec::grml(state_onehot, i), sig_a));
}
else
{
@ -234,7 +234,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
eq_cell->type = "$eq";
eq_cell->connections["\\A"] = sig_a;
eq_cell->connections["\\B"] = sig_b;
eq_cell->connections["\\Y"] = RTLIL::SigSpec(state_onehot, 1, i);
eq_cell->connections["\\Y"] = RTLIL::SigSpec::grml(state_onehot, i);
eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size());
@ -266,7 +266,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
fullstate_cache.erase(tr.state_in);
}
implement_pattern_cache(module, pattern_cache, fullstate_cache, fsm_data.state_table.size(), state_onehot, ctrl_in, RTLIL::SigSpec(next_state_onehot, 1, i));
implement_pattern_cache(module, pattern_cache, fullstate_cache, fsm_data.state_table.size(), state_onehot, ctrl_in, RTLIL::SigSpec::grml(next_state_onehot, i));
}
if (encoding_is_onehot)
@ -279,7 +279,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
if (state.bits[j] == RTLIL::State::S1)
bit_idx = j;
if (bit_idx >= 0)
next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, 1, i));
next_state_sig.replace(bit_idx, RTLIL::SigSpec::grml(next_state_onehot, i));
}
log_assert(!next_state_sig.has_marked_bits());
module->connections.push_back(RTLIL::SigSig(next_state_wire, next_state_sig));
@ -297,7 +297,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
sig_a = RTLIL::SigSpec(state);
} else {
sig_b.append(RTLIL::SigSpec(state));
sig_s.append(RTLIL::SigSpec(next_state_onehot, 1, i));
sig_s.append(RTLIL::SigSpec::grml(next_state_onehot, i));
}
}

2
passes/memory/memory_share.cc
View file

@ -613,7 +613,7 @@ struct MemoryShareWorker
groups_en[key] = grouped_en->width;
grouped_en->width++;
}
en.append(RTLIL::SigSpec(grouped_en, 1, groups_en[key]));
en.append(RTLIL::SigSpec::grml(grouped_en, groups_en[key]));
}
module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);

2
passes/opt/opt_clean.cc
View file

@ -189,7 +189,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
for (auto &it : module->wires) {
RTLIL::Wire *wire = it.second;
for (int i = 0; i < wire->width; i++) {
RTLIL::SigSpec s1 = RTLIL::SigSpec(wire, 1, i), s2 = assign_map(s1);
RTLIL::SigSpec s1 = RTLIL::SigSpec::grml(wire, i), s2 = assign_map(s1);
if (!compare_signals(s1, s2, register_signals, connected_signals, direct_wires))
assign_map.add(s1);
}

4
passes/proc/proc_mux.cc
View file

@ -81,7 +81,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1))
{
mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, 1, cmp_wire->width++), sig));
mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec::grml(cmp_wire, cmp_wire->width++), sig));
}
else
{
@ -103,7 +103,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
eq_cell->connections["\\A"] = sig;
eq_cell->connections["\\B"] = comp;
eq_cell->connections["\\Y"] = RTLIL::SigSpec(cmp_wire, 1, cmp_wire->width++);
eq_cell->connections["\\Y"] = RTLIL::SigSpec::grml(cmp_wire, cmp_wire->width++);
}
}

4
passes/sat/eval.cc
View file

@ -260,8 +260,8 @@ struct VlogHammerReporter
for (int i = 0; i < int(inputs.size()); i++) {
RTLIL::Wire *wire = module->wires.at(inputs[i]);
for (int j = input_widths[i]-1; j >= 0; j--) {
ce.set(RTLIL::SigSpec(wire, 1, j), bits.back());
recorded_set_vars.append(RTLIL::SigSpec(wire, 1, j));
ce.set(RTLIL::SigSpec::grml(wire, j), bits.back());
recorded_set_vars.append(RTLIL::SigSpec::grml(wire, j));
recorded_set_vals.bits.push_back(bits.back());
bits.pop_back();
}

2
passes/sat/miter.cc
View file

@ -174,7 +174,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
eqx_cell->parameters["\\Y_WIDTH"] = 1;
eqx_cell->parameters["\\A_SIGNED"] = 0;
eqx_cell->parameters["\\B_SIGNED"] = 0;
eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, 1, i);
eqx_cell->connections["\\A"] = RTLIL::SigSpec::grml(w2_gold, i);
eqx_cell->connections["\\B"] = RTLIL::State::Sx;
eqx_cell->connections["\\Y"] = gold_x.extract(i, 1);
miter_module->add(eqx_cell);

10
passes/sat/share.cc
View file

@ -292,8 +292,8 @@ struct ShareWorker
supercell->connections["\\Y"] = y;
module->add(supercell);
RTLIL::SigSpec new_y1(y, y1.size(), 0);
RTLIL::SigSpec new_y2(y, y2.size(), 0);
RTLIL::SigSpec new_y1 = RTLIL::SigSpec::grml(y, 0, y1.size());
RTLIL::SigSpec new_y2 = RTLIL::SigSpec::grml(y, 0, y2.size());
module->connections.push_back(RTLIL::SigSig(y1, new_y1));
module->connections.push_back(RTLIL::SigSig(y2, new_y2));
@ -405,8 +405,8 @@ struct ShareWorker
supercell->connections["\\Y"] = y;
supercell->check();
RTLIL::SigSpec new_y1(y, y1.size(), 0);
RTLIL::SigSpec new_y2(y, y2.size(), 0);
RTLIL::SigSpec new_y1 = RTLIL::SigSpec::grml(y, 0, y1.size());
RTLIL::SigSpec new_y2 = RTLIL::SigSpec::grml(y, 0, y2.size());
module->connections.push_back(RTLIL::SigSig(y1, new_y1));
module->connections.push_back(RTLIL::SigSig(y2, new_y2));
@ -620,7 +620,7 @@ struct ShareWorker
RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0);
for (auto &p : activation_patterns) {
all_cases_wire->width++;
module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, 1, all_cases_wire->width - 1));
module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec::grml(all_cases_wire, all_cases_wire->width - 1));
}
if (all_cases_wire->width == 1)
return all_cases_wire;

2
passes/techmap/extract.cc
View file

@ -315,7 +315,7 @@ namespace
RTLIL::Wire *wire = it.second;
if (wire->port_id > 0) {
for (int i = 0; i < wire->width; i++)
sig2port.insert(sigmap(RTLIL::SigSpec(wire, 1, i)), std::pair<std::string, int>(wire->name, i));
sig2port.insert(sigmap(RTLIL::SigSpec::grml(wire, i)), std::pair<std::string, int>(wire->name, i));
cell->connections[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width);
}
}

4
passes/techmap/iopadmap.cc
View file

@ -179,9 +179,9 @@ struct IopadmapPass : public Pass {
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = RTLIL::escape_id(celltype);
cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, 1, i);
cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec::grml(wire, i);
if (!portname2.empty())
cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, 1, i);
cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec::grml(new_wire, i);
if (!widthparam.empty())
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
if (!nameparam.empty())