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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3

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This commit is contained in:
Clifford Wolf 2014-07-23 08:40:31 +02:00
parent 260c19ec5a
commit a8d3a68971
15 changed files with 33 additions and 47 deletions
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4
backends/blif/blif.cc
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@ -118,7 +118,7 @@ struct BlifDumper
for (auto &it : inputs) {
RTLIL::Wire *wire = it.second;
for (int i = 0; i < wire->width; i++)
fprintf(f, " %s", cstr(RTLIL::SigSpec(wire, 1, i)));
fprintf(f, " %s", cstr(RTLIL::SigSpec::grml(wire, i)));
}
fprintf(f, "\n");
@ -126,7 +126,7 @@ struct BlifDumper
for (auto &it : outputs) {
RTLIL::Wire *wire = it.second;
for (int i = 0; i < wire->width; i++)
fprintf(f, " %s", cstr(RTLIL::SigSpec(wire, 1, i)));
fprintf(f, " %s", cstr(RTLIL::SigSpec::grml(wire, i)));
}
fprintf(f, "\n");

2
backends/edif/edif.cc
View file

@ -271,7 +271,7 @@ struct EdifBackend : public Backend {
} else {
fprintf(f, " (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir);
for (int i = 0; i < wire->width; i++) {
RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, 1, i));
RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec::grml(wire, i));
net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i));
}
}