diff --git a/tests/various/check_nolatches.ys b/tests/various/check_nolatches.ys
index 3cc854c87..9c45c6bb9 100644
--- a/tests/various/check_nolatches.ys
+++ b/tests/various/check_nolatches.ys
@@ -1,8 +1,10 @@
-read_verilog <<EOT
+design -reset
+read -vlog2k <<EOT
 module top(input g, rn, d, output reg q);
 always @* if (~rn) q <= 0; else if (g) q <= d;
 endmodule
 EOT
+hierarchy -top top
 proc
 select -assert-count 1 t:$dlatch
 logger -expect warning "is a latch of type" 1
@@ -10,24 +12,25 @@ check -nolatches
 logger -check-expected
 
 design -reset
-
-read_verilog <<EOT
+read -vlog2k <<EOT
 module top(input g, d, output reg q);
 always @* q = g ? d : 1'b0;
 endmodule
 EOT
+hierarchy -top top
 proc
 check -nolatches -assert
 
 design -reset
 
-read_verilog <<EOT
+read -vlog2k <<EOT
 module top(input g, d, output reg q, output y);
 always @* if (g) q = d;
 wire u;
 assign y = u;
 endmodule
 EOT
+hierarchy -top top
 proc
 logger -expect error "Found 1 problems in" 1
 check -latchonly -assert