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Make log() use the FmtString infrastructure.

Browse source 
Now `log()` supports `std::string`.

We have to fix a few places where the format parameter was not a compile time constant.
This is mostly trivial.
This commit is contained in:
Robert O'Callahan 2025-07-10 05:24:59 +00:00 • committed by Jannis Harder
parent c6e96d7816
commit a8791a459e
10 changed files with 74 additions and 45 deletions
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10
passes/cmds/logcmd.cc
View file

@ -101,13 +101,13 @@ struct LogPass : public Pass {
text += args[argidx] + ' ';
if (!text.empty()) text.resize(text.size()-1);
const char *fmtline = newline ? "%s\n" : "%s";
const char *line_end = newline ? "\n" : "";
if (to_stdout) fprintf(stdout, fmtline, text.c_str());
if (to_stderr) fprintf(stderr, fmtline, text.c_str());
if (to_stdout) fprintf(stdout, "%s%s", text.c_str(), line_end);
if (to_stderr) fprintf(stderr, "%s%s", text.c_str(), line_end);
if (to_log) {
if (!header) log(fmtline, text.c_str());
else log_header(design, fmtline, text.c_str());
if (!header) log("%s%s", text.c_str(), line_end);
else log_header(design, "%s%s", text.c_str(), line_end);
}
}
} LogPass;

2
passes/cmds/stat.cc
View file

@ -1017,7 +1017,7 @@ struct StatPass : public Pass {
if (json_mode) {
log("\n");
log(top_mod == nullptr ? " }\n" : " },\n");
log("%s", top_mod == nullptr ? " }\n" : " },\n");
}
if (top_mod != nullptr) {

2
passes/equiv/equiv_simple.cc
View file

@ -331,7 +331,7 @@ struct EquivSimpleWorker
construct_ezsat(input_bits, step);
if (!ez->solve(ez_context)) {
log(cfg.verbose ? " Proved equivalence! Marking $equiv cell as proven.\n" : " success!\n");
log("%s", cfg.verbose ? " Proved equivalence! Marking $equiv cell as proven.\n" : " success!\n");
// Replace $equiv cell with a short
cell->setPort(ID::B, cell->getPort(ID::A));
ez->assume(ez->NOT(ez_context));

4
passes/sat/sat.cc
View file

@ -634,10 +634,10 @@ struct SatHelper
"---------------------------------------------------------------------------------------------------"
"---------------------------------------------------------------------------------------------------";
if (last_timestep == -2) {
log(max_timestep > 0 ? " Time " : " ");
log("%s", max_timestep > 0 ? " Time " : " ");
log("%-*s %11s %9s %*s\n", maxModelName+5, "Signal Name", "Dec", "Hex", maxModelWidth+3, "Bin");
}
log(max_timestep > 0 ? " ---- " : " ");
log("%s", max_timestep > 0 ? " ---- " : " ");
log("%*.*s %11.11s %9.9s %*.*s\n", maxModelName+5, maxModelName+5,
hline, hline, hline, maxModelWidth+3, maxModelWidth+3, hline);
last_timestep = info.timestep;

14
passes/techmap/dfflibmap.cc
View file

@ -135,7 +135,7 @@ static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std
if (ff == nullptr || ff->args.size() != 2)
return false;
auto ff_output = ff->args.at(0);
// This test is redundant with the one in enable_pin, but we're in a
// position that gives better diagnostics here.
if (!pin_names.count(ff_output)) {
@ -166,23 +166,23 @@ static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std
// the ff output Q is in a known bit location, so we now just have to compare the LUT mask to known values to find the enable pin and polarity.
if (lut == 0xD8) {
data_name = pins[1];
enable_name = pins[0];
enable_name = pins[0];
return true;
}
if (lut == 0xB8) {
data_name = pins[0];
enable_name = pins[1];
enable_name = pins[1];
return true;
}
enable_not_inverted = false;
if (lut == 0xE4) {
data_name = pins[1];
enable_name = pins[0];
enable_name = pins[0];
return true;
}
if (lut == 0xE2) {
data_name = pins[0];
enable_name = pins[1];
enable_name = pins[1];
return true;
}
// this does not match an enable flop.
@ -553,11 +553,11 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
new_cell->setPort("\\" + port.first, sig);
}
stats[stringf(" mapped %%d %s cells to %s cells.\n", cell_type, new_cell->type)]++;
stats[stringf("%s cells to %s cells", cell_type, new_cell->type)]++;
}
for (auto &stat: stats)
log(stat.first.c_str(), stat.second);
log(" mapped %d %s.\n", stat.second, stat.first);
}
struct DfflibmapPass : public Pass {

2
passes/tests/test_cell.cc
View file

@ -620,7 +620,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
for (int i = 0; i < 64; i++)
{
log(verbose ? "\n" : ".");
log("%s", verbose ? "\n" : ".");
gold_ce.clear();
gate_ce.clear();