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Initial support for extraction of counters with clock enable
This commit is contained in:
Andrew Zonenberg
parent
c4a70a8cc3
commit
a84172b23b
2 changed files with 131 additions and 30 deletions
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@ -92,9 +92,11 @@ struct CounterExtraction
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int width; //counter width
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RTLIL::Wire* rwire; //the register output
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bool has_reset; //true if we have a reset
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bool has_ce; //true if we have a clock enable
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RTLIL::SigSpec rst; //reset pin
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int count_value; //value we count from
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RTLIL::SigSpec clk; //clock signal
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RTLIL::SigSpec ce; //clock signal
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RTLIL::SigSpec clk; //clock enable, if any
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RTLIL::SigSpec outsig; //counter output signal
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RTLIL::Cell* count_mux; //counter mux
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RTLIL::Cell* count_reg; //counter register
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@ -190,12 +192,43 @@ int counter_tryextract(
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return 13;
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extract.underflow_inv = underflow_inv;
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//Y connection of the mux must have exactly one load, the counter's internal register
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//Y connection of the mux must have exactly one load, the counter's internal register, if there's no clock enable
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//If we have a clock enable, Y drives the B input of a mux. A of that mux must come from our register
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const RTLIL::SigSpec muxy = sigmap(count_mux->getPort("\\Y"));
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pool<Cell*> muxy_loads = get_other_cells(muxy, index, count_mux);
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if(muxy_loads.size() != 1)
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return 14;
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Cell* count_reg = *muxy_loads.begin();
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Cell* muxload = *muxy_loads.begin();
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Cell* count_reg = muxload;
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Cell* cemux = NULL;
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RTLIL::SigSpec cey;
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if(muxload->type == "$mux")
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{
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//This mux is probably a clock enable mux.
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//Find our count register (should be our only load)
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cemux = muxload;
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cey = sigmap(cemux->getPort("\\Y"));
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pool<Cell*> cey_loads = get_other_cells(cey, index, cemux);
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if(cey_loads.size() != 1)
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return 24;
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count_reg = *cey_loads.begin();
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//Mux should have A driven by count Q, and B by muxy
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//TODO: if A and B are swapped, CE polarity is inverted
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if(sigmap(cemux->getPort("\\B")) != muxy)
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return 24;
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if(sigmap(cemux->getPort("\\A")) != sigmap(count_reg->getPort("\\Q")))
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return 24;
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if(sigmap(cemux->getPort("\\Y")) != sigmap(count_reg->getPort("\\D")))
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return 24;
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//Select of the mux is our clock enable
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extract.has_ce = true;
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extract.ce = sigmap(cemux->getPort("\\S"));
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}
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else
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extract.has_ce = false;
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extract.count_reg = count_reg;
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if(count_reg->type == "$dff")
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extract.has_reset = false;
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@ -216,17 +249,30 @@ int counter_tryextract(
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//TODO: support synchronous reset
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else
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return 15;
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if(!is_full_bus(muxy, index, count_mux, "\\Y", count_reg, "\\D"))
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//Sanity check that we use the ALU output properly
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if(extract.has_ce)
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{
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if(!is_full_bus(muxy, index, count_mux, "\\Y", cemux, "\\B"))
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return 16;
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if(!is_full_bus(cey, index, cemux, "\\Y", count_reg, "\\D"))
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return 16;
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}
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else if(!is_full_bus(muxy, index, count_mux, "\\Y", count_reg, "\\D"))
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return 16;
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//TODO: Verify count_reg CLK_POLARITY is 1
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//Register output must have exactly two loads, the inverter and ALU
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//(unless we have a parallel output!)
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//If we have a clock enable, 3 is OK
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const RTLIL::SigSpec qport = count_reg->getPort("\\Q");
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const RTLIL::SigSpec cnout = sigmap(qport);
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pool<Cell*> cnout_loads = get_other_cells(cnout, index, count_reg);
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if(cnout_loads.size() > 2)
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unsigned int max_loads = 2;
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if(extract.has_ce)
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max_loads = 3;
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if(cnout_loads.size() > max_loads)
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{
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//If we specified a limited set of cells for parallel output, check that we only drive them
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if(!parallel_cells.empty())
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@ -237,6 +283,8 @@ int counter_tryextract(
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continue;
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if(c == cell)
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continue;
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if(c == muxload)
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continue;
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//Make sure we're in the whitelist
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if( parallel_cells.find(c->type) == parallel_cells.end())
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@ -346,7 +394,7 @@ void counter_worker(
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//Do nothing, unless extraction was forced in which case give an error
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if(reason != 0)
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{
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static const char* reasons[24]=
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static const char* reasons[25]=
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{
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"no problem", //0
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"counter is too large/small", //1
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@ -371,7 +419,8 @@ void counter_worker(
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"No init value found", //20
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"Underflow value is not equal to init value", //21
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"Reset polarity is not positive", //22
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"Reset is not to zero" //23
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"Reset is not to zero", //23
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"Clock enable configuration is unsupported" //24
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};
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if(force_extract)
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@ -424,9 +473,17 @@ void counter_worker(
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cell->setPort("\\CLK", extract.clk);
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cell->setPort("\\OUT", extract.outsig);
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//Hook up hard-wired ports (for now CE and up/down are not supported), default to no parallel output
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cell->setParam("\\HAS_POUT", RTLIL::Const(0));
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//Hook up clock enable
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if(extract.has_ce)
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{
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cell->setParam("\\HAS_CE", RTLIL::Const(1));
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cell->setPort("\\CE", extract.ce);
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}
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else
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cell->setParam("\\HAS_CE", RTLIL::Const(0));
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//Hook up hard-wired ports (for now up/down are not supported), default to no parallel output
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cell->setParam("\\HAS_POUT", RTLIL::Const(0));
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cell->setParam("\\DIRECTION", RTLIL::Const("DOWN"));
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cell->setPort("\\CE", RTLIL::Const(1));
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cell->setPort("\\UP", RTLIL::Const(0));
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@ -161,8 +161,8 @@ module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
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parameter WIDTH = 8;
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parameter DIRECTION = "DOWN";
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//If we have a CE, or DIRECTION other than DOWN fail... GP_COUNTx_ADV is not supported yet
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if(HAS_CE || (DIRECTION != "DOWN") ) begin
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//If we have a DIRECTION other than DOWN fail... GP_COUNTx_ADV is not supported yet
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if(DIRECTION != "DOWN") begin
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initial begin
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$display("ERROR: \$__COUNT_ support for GP_COUNTx_ADV is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?).");
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$finish;
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@ -187,6 +187,27 @@ module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
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//Looks like a legal counter! Do something with it
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else if(WIDTH <= 8) begin
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if(HAS_CE) begin
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wire ce_not;
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GP_INV ceinv(
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.IN(CE),
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.OUT(ce_not)
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);
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GP_COUNT8_ADV #(
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.COUNT_TO(COUNT_TO),
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.RESET_MODE(RESET_MODE),
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.RESET_VALUE("COUNT_TO"),
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.CLKIN_DIVIDE(1)
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) _TECHMAP_REPLACE_ (
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.CLK(CLK),
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.RST(RST),
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.OUT(OUT),
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.UP(1'b0), //always count down for now
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.KEEP(ce_not),
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.POUT(POUT)
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);
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end
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else begin
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GP_COUNT8 #(
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.COUNT_TO(COUNT_TO),
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.RESET_MODE(RESET_MODE),
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@ -198,7 +219,29 @@ module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
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.POUT(POUT)
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);
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end
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end
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else begin
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if(HAS_CE) begin
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wire ce_not;
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GP_INV ceinv(
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.IN(CE),
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.OUT(ce_not)
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);
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GP_COUNT14_ADV #(
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.COUNT_TO(COUNT_TO),
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.RESET_MODE(RESET_MODE),
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.RESET_VALUE("COUNT_TO"),
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.CLKIN_DIVIDE(1)
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) _TECHMAP_REPLACE_ (
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.CLK(CLK),
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.RST(RST),
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.OUT(OUT),
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.UP(1'b0), //always count down for now
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.KEEP(ce_not),
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.POUT(POUT)
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);
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end
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else begin
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GP_COUNT14 #(
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.COUNT_TO(COUNT_TO),
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@ -210,5 +253,6 @@ module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
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.OUT(OUT)
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);
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end
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end
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endmodule
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