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Make test without iopads
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parent
509da7ed1a
commit
a82c701668
17 changed files with 51 additions and 51 deletions
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@ -3,7 +3,7 @@ design -save read
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hierarchy -top mux2
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proc
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux2 # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT3
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@ -14,7 +14,7 @@ select -assert-none t:LUT3 %% t:* %D
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design -load read
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hierarchy -top mux4
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proc
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux4 # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT6
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@ -25,7 +25,7 @@ select -assert-none t:LUT6 %% t:* %D
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design -load read
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hierarchy -top mux8
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proc
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux8 # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT3
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@ -37,7 +37,7 @@ select -assert-none t:LUT3 t:LUT6 %% t:* %D
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design -load read
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hierarchy -top mux16
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proc
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux16 # Constrain all select calls below inside the top module
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select -assert-min 5 t:LUT6
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