mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-10 13:10:51 +00:00
Code Activity

Make test without iopads

Browse source
This commit is contained in:
Miodrag Milanovic 2019-12-28 16:22:24 +01:00
parent 509da7ed1a
commit a82c701668
17 changed files with 51 additions and 51 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tests/arch/xilinx/mul.ys
View file

@ -1,7 +1,7 @@
read_verilog ../common/mul.v
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module