mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-26 21:16:03 +00:00
Code Activity

Make test without iopads

Browse source
This commit is contained in:
Miodrag Milanovic 2019-12-28 16:22:24 +01:00
parent 509da7ed1a
commit a82c701668
17 changed files with 51 additions and 51 deletions
Download patch file Download diff file Expand all files Collapse all files

14
tests/arch/xilinx/lutram.ys
View file

@ -2,7 +2,7 @@
#hierarchy -top lutram_1w1r -chparam A_WIDTH 4
#proc
#memory -nomap
#equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
#equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
#memory
#opt -full
#
@ -22,7 +22,7 @@ read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r -chparam A_WIDTH 5
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
memory
opt -full
@ -42,7 +42,7 @@ read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
memory
opt -full
@ -62,7 +62,7 @@ read_verilog ../common/lutram.v
hierarchy -top lutram_1w3r
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
memory
opt -full
@ -82,7 +82,7 @@ read_verilog ../common/lutram.v
hierarchy -top lutram_1w3r -chparam A_WIDTH 6
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
memory
opt -full
@ -102,7 +102,7 @@ read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 6
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
memory
opt -full
@ -122,7 +122,7 @@ read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r -chparam A_WIDTH 6 -chparam D_WIDTH 6
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
memory
opt -full