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A few modifications after pull request comments

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- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
This commit is contained in:
Ruben Undheim 2016-06-18 14:13:36 +02:00
parent 178ff3e7f6
commit a8200a773f
3 changed files with 4 additions and 5 deletions
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4
frontends/ast/ast.cc
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@ -997,7 +997,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
for (auto n : global_decls)
(*it)->children.push_back(n->clone());
for (auto n : design->packages){
for (auto n : design->verilog_packages){
for (auto o : n->children) {
AstNode *cloned_node = o->clone();
cloned_node->str = n->str + std::string("::") + cloned_node->str.substr(1);
@ -1023,7 +1023,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
design->add(process_module(*it, defer));
}
else if ((*it)->type == AST_PACKAGE){
design->packages.push_back((*it)->clone());
design->verilog_packages.push_back((*it)->clone());
}
else
global_decls.push_back(*it);