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This commit is contained in:
Eddie Hung 2020-01-03 14:59:55 -08:00
parent 559f3379e8
commit a819656972
3 changed files with 7 additions and 63 deletions
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2
passes/techmap/abc9_ops.cc
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@ -386,8 +386,6 @@ void prep_holes(RTLIL::Module *module)
}
}
// NB: Assume box_module->ports are sorted alphabetically
// (as RTLIL::Module::fixup_ports() would do)
for (const auto &port_name : box_ports.at(cell->type)) {
RTLIL::Wire *w = box_module->wire(port_name);
log_assert(w);