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This commit is contained in:
Eddie Hung 2020-01-03 14:59:55 -08:00
parent 559f3379e8
commit a819656972
3 changed files with 7 additions and 63 deletions
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12
passes/techmap/abc9.cc
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@ -186,15 +186,17 @@ struct Abc9Pass : public ScriptPass
void script() YS_OVERRIDE
{
run("scc -set_attr abc9_scc_id {}");
run("abc9_ops -break_scc"/*" -prep_holes"*/);
// run("flatten -wb @abc9_holes");
// run("techmap @abc9_holes");
run("abc9_ops -break_scc");
run("aigmap");
run("abc9_ops -prep_holes");
run("select -set abc9_holes A:abc9_holes");
run("flatten -wb @abc9_holes");
run("techmap @abc9_holes");
run("aigmap @abc9_holes");
if (dff_mode)
run("abc9_ops -prep_dff");
// run("opt -purge @abc9_holes");
run("select -set abc9_holes A:abc9_holes");
run("opt -purge @abc9_holes");
run("wbflip @abc9_holes");
auto selected_modules = active_design->selected_modules();

2
passes/techmap/abc9_ops.cc
View file

@ -386,8 +386,6 @@ void prep_holes(RTLIL::Module *module)
}
}
// NB: Assume box_module->ports are sorted alphabetically
// (as RTLIL::Module::fixup_ports() would do)
for (const auto &port_name : box_ports.at(cell->type)) {
RTLIL::Wire *w = box_module->wire(port_name);
log_assert(w);