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https://github.com/YosysHQ/yosys
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Add sub chain support for csa trees.
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nella
parent
b6ea0bb4cc
commit
a7fcfc18fa
1 changed files with 123 additions and 34 deletions
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@ -13,7 +13,7 @@ struct CsaTreeWorker
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dict<SigBit, pool<Cell*>> bit_consumers;
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dict<SigBit, int> fanout;
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pool<Cell*> all_adds;
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pool<Cell*> all_addsubs;
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CsaTreeWorker(Module *module) : module(module), sigmap(module) {}
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@ -22,11 +22,11 @@ struct CsaTreeWorker
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int depth;
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};
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void find_adds()
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void find_addsubs()
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{
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for (auto cell : module->cells())
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if (cell->type == ID($add))
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all_adds.insert(cell);
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if (cell->type == ID($add) || cell->type == ID($sub))
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all_addsubs.insert(cell);
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}
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void build_fanout_map()
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@ -46,9 +46,9 @@ struct CsaTreeWorker
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fanout[bit]++;
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}
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Cell*single_add_consumer(SigSpec sig)
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Cell* single_addsub_consumer(SigSpec sig)
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{
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Cell*consumer = nullptr;
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Cell* consumer = nullptr;
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for (auto bit : sig) {
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if (!fanout.count(bit) || fanout[bit] != 1)
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@ -57,7 +57,7 @@ struct CsaTreeWorker
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return nullptr;
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Cell* c = *bit_consumers[bit].begin();
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if (!all_adds.count(c))
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if (!all_addsubs.count(c))
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return nullptr;
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if (consumer == nullptr)
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@ -69,13 +69,13 @@ struct CsaTreeWorker
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return consumer;
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}
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dict<Cell*, Cell*> find_add_parents()
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dict<Cell*, Cell*> find_addsub_parents()
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{
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dict<Cell*, Cell*> parent_of;
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for (auto cell : all_adds) {
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for (auto cell : all_addsubs) {
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SigSpec y = sigmap(cell->getPort(ID::Y));
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Cell* consumer = single_add_consumer(y);
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Cell* consumer = single_addsub_consumer(y);
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if (consumer != nullptr && consumer != cell)
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parent_of[cell] = consumer;
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}
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@ -125,22 +125,78 @@ struct CsaTreeWorker
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struct Operand {
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SigSpec sig;
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bool is_signed;
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bool negate;
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};
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std::vector<Operand> collect_leaf_operands(const pool<Cell*> &chain, const pool<SigBit> &chain_y_bits)
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bool is_subtracted_input(Cell* child, Cell* parent)
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{
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if (parent->type != ID($sub))
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return false;
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SigSpec child_y = sigmap(child->getPort(ID::Y));
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SigSpec parent_b = sigmap(parent->getPort(ID::B));
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for (auto bit : child_y)
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for (auto pbit : parent_b)
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if (bit == pbit)
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return true;
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return false;
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}
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std::vector<Operand> collect_leaf_operands(
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const pool<Cell*> &chain,
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const pool<SigBit> &chain_y_bits,
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Cell* root,
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const dict<Cell*, Cell*> &parent_of,
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int &correction
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) {
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dict<Cell*, bool> negated;
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negated[root] = false;
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std::queue<Cell*> worklist;
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worklist.push(root);
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while (!worklist.empty()) {
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Cell* cur = worklist.front();
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worklist.pop();
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for (auto cell : chain) {
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if (!parent_of.count(cell))
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continue;
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if (parent_of.at(cell) != cur)
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continue;
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if (negated.count(cell))
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continue;
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bool sub_b = is_subtracted_input(cell, cur);
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negated[cell] = negated[cur] ^ sub_b;
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worklist.push(cell);
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}
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}
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std::vector<Operand> operands;
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correction = 0;
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for (auto cell : chain) {
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bool cell_neg = negated.count(cell) ? negated[cell] : false;
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SigSpec a = sigmap(cell->getPort(ID::A));
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SigSpec b = sigmap(cell->getPort(ID::B));
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bool a_signed = cell->getParam(ID::A_SIGNED).as_bool();
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bool b_signed = cell->getParam(ID::B_SIGNED).as_bool();
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bool b_subtracted = (cell->type == ID($sub));
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if (!is_chain_internal(a, chain_y_bits))
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operands.push_back({a, a_signed});
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if (!is_chain_internal(b, chain_y_bits))
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operands.push_back({b, b_signed});
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if (!is_chain_internal(a, chain_y_bits)) {
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bool neg_a = cell_neg;
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operands.push_back({a, a_signed, neg_a});
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if (neg_a)
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correction++;
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}
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if (!is_chain_internal(b, chain_y_bits)) {
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bool neg_b = cell_neg ^ b_subtracted;
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operands.push_back({b, b_signed, neg_b});
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if (neg_b)
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correction++;
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}
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}
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return operands;
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@ -157,6 +213,23 @@ struct CsaTreeWorker
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return sig;
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}
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SigSpec emit_not(SigSpec sig, int width)
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{
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SigSpec out = module->addWire(NEW_ID, width);
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Cell* inv = module->addCell(NEW_ID, ID($not));
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inv->setParam(ID::A_SIGNED, false);
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inv->setParam(ID::A_WIDTH, width);
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inv->setParam(ID::Y_WIDTH, width);
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inv->setPort(ID::A, sig);
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inv->setPort(ID::Y, out);
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return out;
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}
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SigSpec make_constant(int value, int width)
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{
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return SigSpec(value, width);
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}
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std::pair<SigSpec, SigSpec> emit_fa(SigSpec a, SigSpec b, SigSpec c, int width)
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{
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SigSpec sum = module->addWire(NEW_ID, width);
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@ -247,13 +320,13 @@ struct CsaTreeWorker
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void run()
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{
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find_adds();
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if (all_adds.empty())
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find_addsubs();
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if (all_addsubs.empty())
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return;
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build_fanout_map();
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auto parent_of = find_add_parents();
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auto parent_of = find_addsub_parents();
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pool<Cell*> has_parent;
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dict<Cell*, pool<Cell*>> children_of;
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@ -264,7 +337,7 @@ struct CsaTreeWorker
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pool<Cell*> processed;
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for (auto root : all_adds)
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for (auto root : all_addsubs)
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{
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if (has_parent.count(root))
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continue;
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@ -279,23 +352,40 @@ struct CsaTreeWorker
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processed.insert(c);
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pool<SigBit> chain_y_bits = collect_chain_outputs(chain);
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auto operands = collect_leaf_operands(chain, chain_y_bits);
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int correction = 0;
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auto operands = collect_leaf_operands(chain, chain_y_bits, root, parent_of, correction);
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if (operands.size() < 3)
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continue;
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SigSpec root_y = root->getPort(ID::Y);
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int width = GetSize(root_y);
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std::vector<SigSpec> extended;
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for (auto &op : operands)
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extended.push_back(extend_to(op.sig, op.is_signed, width));
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for (auto &op : operands) {
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SigSpec s = extend_to(op.sig, op.is_signed, width);
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if (op.negate)
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s = emit_not(s, width);
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extended.push_back(s);
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}
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if (correction > 0)
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extended.push_back(make_constant(correction, width));
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int fa_count;
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auto [final_a, final_b] = build_wallace_tree(extended, width, fa_count);
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int num_subs = 0;
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log(" Replaced chain of %d $add cells with %d $fa + 1 $add (%d operands, module %s)\n",
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(int)chain.size(), fa_count, (int)operands.size(), log_id(module));
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for (auto cell : chain)
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if (cell->type == ID($sub))
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num_subs++;
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if (num_subs > 0)
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log(" Replaced chain of %d $add/%d $sub cells with %d $fa + 1 $add (%d operands, module %s)\n",
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(int)chain.size() - num_subs, num_subs, fa_count, (int)operands.size(), log_id(module));
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else
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log(" Replaced chain of %d $add cells with %d $fa + 1 $add (%d operands, module %s)\n",
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(int)chain.size(), fa_count, (int)operands.size(), log_id(module));
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emit_final_add(final_a, final_b, root_y, width);
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@ -306,22 +396,21 @@ struct CsaTreeWorker
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};
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struct CsaTreePass : public Pass {
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CsaTreePass() : Pass("csa_tree", "convert $add chains to carry-save adder trees") {}
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CsaTreePass() : Pass("csa_tree", "convert $add/$sub chains to carry-save adder trees") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" csa_tree [selection]\n");
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log("\n");
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log("This pass finds chains of $add cells and replaces them with\n");
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log("carry-save adder (CSA) trees built from $fa cells, followed by\n");
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log("a single final $add for the carry-propagate step.\n");
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log("This pass finds chains of $add and $sub cells and replaces them with carry-save\n");
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log("adder trees built from $fa cells, followed by a single final $add for the\n");
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log("carry-propagate step.\n");
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log("\n");
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log("The tree uses Wallace-tree scheduling for optimal depth:\n");
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log("at each level, all ready operands are grouped into triplets\n");
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log("and compressed via full adders. This gives ceil(log_1.5(N))\n");
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log("FA levels for N input operands.\n");
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log("The tree uses Wallace-tree scheduling for optimal depth: at each level, all ready\n");
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log("operands are grouped into triplets and compressed via full adders. This\n");
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log("gives ceil(log_1.5(N)) FA levels for N input operands.\n");
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log("\n");
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}
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