Add check_mem command

Comes with a set of tests which (currently) pass with `read_verilog` but fail with `verific` based on #5878.
Add `--check-sv`, an alternative to `--prove-sv` with generator defined yosys commands.  Helpful for when you want to run the same set of commands on a bunch of sv files.

tests/check_mem/non_zero.sv

@@ -0,0 +1,21 @@
+module top (
+  input logic clk,
+  input logic [3:1][2:0] in_data,
+  output logic [3:1][2:0] out_data
+);
+  (* nomem2reg *)
+  logic [2:0] my_array [3:1];
+
+  always_ff @(posedge clk) begin
+    for (int i = 1; i <= 3; i++) begin
+      my_array[i] <= in_data[i];
+    end
+  end
+
+  always_comb begin
+    for (int i = 1; i <= 3; i++) begin
+      out_data[i] = my_array[i];
+    end
+  end
+
+endmodule