Add check_mem command

Comes with a set of tests which (currently) pass with `read_verilog` but fail with `verific` based on #5878.
Add `--check-sv`, an alternative to `--prove-sv` with generator defined yosys commands.  Helpful for when you want to run the same set of commands on a bunch of sv files.

tests/check_mem/init.sv

@@ -0,0 +1,15 @@
+module top (
+  input logic clk,
+  input logic idx,
+  output logic [2:0] out_data
+);
+  (* nomem2reg *)
+  logic my_array [3:2][2:0] = '{'{0, 1, 1}, '{1, 0, 1}};
+
+  always_comb begin
+    for (int i=0; i < 3; i++) begin
+        out_data[i] = my_array[{1'b1, idx}][i];
+    end
+  end
+
+endmodule