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Added "read_verilog -dump_rtlil"
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8537c4d206
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5 changed files with 38 additions and 9 deletions
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@ -187,7 +187,7 @@ namespace AST
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int linenum;
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// creating and deleting nodes
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AstNode(AstNodeType type = AST_NONE, AstNode *child1 = NULL, AstNode *child2 = NULL);
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AstNode(AstNodeType type = AST_NONE, AstNode *child1 = NULL, AstNode *child2 = NULL, AstNode *child3 = NULL);
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AstNode *clone();
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void cloneInto(AstNode *other);
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void delete_children();
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@ -272,7 +272,8 @@ namespace AST
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};
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// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
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void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire);
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void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit,
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bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire);
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// parametric modules are supported directly by the AST library
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// therefore we need our own derivate of RTLIL::Module with overloaded virtual functions
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@ -302,7 +303,8 @@ namespace AST
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namespace AST_INTERNAL
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{
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// internal state variables
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extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
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extern bool flag_dump_ast1, flag_dump_ast2, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
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extern bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
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extern AST::AstNode *current_ast, *current_ast_mod;
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extern std::map<std::string, AST::AstNode*> current_scope;
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extern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr;
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