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Merge pull request #3992 from YosysHQ/empty-case-fix

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write_verilog: avoid emitting empty cases.
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Lofty 2023-10-08 08:05:10 +01:00 committed by GitHub
parent a1923a5f77 c36cf9c5ac
commit a79b15e947
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backends/verilog/verilog_backend.cc
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@ -2008,6 +2008,11 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
dump_case_body(f, indent + " ", *it); dump_case_body(f, indent + " ", *it);
} }
if (sw->cases.empty()) {
// Verilog does not allow empty cases.
f << stringf("%s default: ;\n", indent.c_str());
}
f << stringf("%s" "endcase\n", indent.c_str()); f << stringf("%s" "endcase\n", indent.c_str());
} }