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Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort

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write_rtlil: don't sort
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Emil J 2025-09-22 11:14:39 +02:00 • committed by GitHub
commit a78eb9e151
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19 changed files with 247 additions and 109 deletions
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Makefile
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@ -890,6 +890,7 @@ MK_TEST_DIRS += tests/sim
MK_TEST_DIRS += tests/svtypes
MK_TEST_DIRS += tests/techmap
MK_TEST_DIRS += tests/various
MK_TEST_DIRS += tests/rtlil
ifeq ($(ENABLE_VERIFIC),1)
ifneq ($(YOSYS_NOVERIFIC),1)
MK_TEST_DIRS += tests/verific