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Fix initialisation of flops

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This commit is contained in:
Eddie Hung 2019-06-15 09:46:35 -07:00
parent 6d74b3e004
commit a76c8a7ffd
3 changed files with 15 additions and 14 deletions
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5
passes/techmap/abc9.cc
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@ -520,8 +520,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
continue;
}
else if (cell->type.in("$_FF_")) {
SigBit D = cell->getPort("\\D");
SigBit Q = cell->getPort("\\Q");
RTLIL::Wire *D = cell->getPort("\\D").as_wire();
RTLIL::Wire *Q = cell->getPort("\\Q").as_wire();
Q->attributes.swap(D->attributes);
module->connect(Q, D);
it = module->cells_.erase(it);
continue;