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Try using an ICE40_CARRY_LUT primitive to avoid ABC issues

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This commit is contained in:
Eddie Hung 2019-04-17 11:10:04 -07:00
parent d59185f1d6
commit a7632ab332
7 changed files with 102 additions and 35 deletions
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24
techlibs/ice40/cells_map.v
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@ -57,3 +57,27 @@ module \$lut (A, Y);
endgenerate
endmodule
`endif
`ifndef NO_CARRY
module ICE40_CARRY_LUT (output CO, O, input CI, I1, I2);
SB_CARRY carry (
.I0(I1),
.I1(I2),
.CI(CI),
.CO(CO),
);
SB_LUT4 #(
// I0: 1010 1010 1010 1010
// I1: 1100 1100 1100 1100
// I2: 1111 0000 1111 0000
// I3: 1111 1111 0000 0000
.LUT_INIT(16'b 0110_1001_1001_0110)
) adder (
.I0(1'b0),
.I1(I1),
.I2(I2),
.I3(CI),
.O(O)
);
endmodule
`endif