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Implemented temporal induction proofs in sat_solve

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Clifford Wolf 2013-06-09 18:07:05 +02:00
parent b210234612
commit a75b249427
3 changed files with 180 additions and 39 deletions
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6
passes/sat/example.ys
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@ -1,11 +1,13 @@
read_verilog example.v
proc; opt_clean
sat_solve -set y 1'b1 example001
sat_solve -set y 1'b1 example002
sat_solve -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003
sat_solve -set y 1'b1 example004
sat_solve -show rst,counter -set-at 3 y 1'b1 -seq 4 example004
sat_solve -prove y 1'b0 example001
# sat_solve -show rst,counter -prove y 1'b0 -set-at 1 rst 1'b1 -seq 1 example004
sat_solve -prove y 1'b0 -show rst,counter,y example004
sat_solve -prove y 1'b0 -show rst,counter,y -set-at 1 rst 1'b1 -seq 1 example004