mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-14 09:56:16 +00:00
Code Activity

Merge pull request #2340 from andy-knowles/cxxrtl-fix-alu-carryout

Browse source 
cxxrtl.h: Fix incorrect CarryOut in alu when Bits % 32 != 0 && Invert == False
This commit is contained in:
whitequark 2020-08-12 20:02:18 +00:00 • committed by GitHub
commit a74a43d85d
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 2 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

3
backends/cxxrtl/cxxrtl.h
View file

@ -452,10 +452,11 @@ struct value : public expr_base<value<Bits>> {
bool carry = CarryIn; bool carry = CarryIn;
for (size_t n = 0; n < result.chunks; n++) { for (size_t n = 0; n < result.chunks; n++) {
result.data[n] = data[n] + (Invert ? ~other.data[n] : other.data[n]) + carry; result.data[n] = data[n] + (Invert ? ~other.data[n] : other.data[n]) + carry;
if (result.chunks - 1 == n)
result.data[result.chunks - 1] &= result.msb_mask;
carry = (result.data[n] < data[n]) || carry = (result.data[n] < data[n]) ||
(result.data[n] == data[n] && carry); (result.data[n] == data[n] && carry);
} }
result.data[result.chunks - 1] &= result.msb_mask;
return {result, carry}; return {result, carry};
} }