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More deadname stuff

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Claire Xenia Wolf 2021-06-09 12:33:41 +02:00
parent 0ada13cbe2
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10 changed files with 27 additions and 27 deletions
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6
manual/PRESENTATION_Intro.tex
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@ -260,7 +260,7 @@ The following slides cover an example project. This project contains three files
\end{itemize}
\vfill
Direct link to the files: \\ \footnotesize
\url{https://github.com/cliffordwolf/yosys/tree/master/manual/PRESENTATION_Intro}
\url{https://github.com/YosysHQ/yosys/tree/master/manual/PRESENTATION_Intro}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@ -806,7 +806,7 @@ but also formal verification, reverse engineering, ...}
\begin{itemize}
\item Ongoing PhD project on coarse grain synthesis \\
{\setlength{\parindent}{0.5cm}\footnotesize
Johann Glaser and Clifford Wolf. Methodology and Example-Driven Interconnect
Johann Glaser and C. Wolf. Methodology and Example-Driven Interconnect
Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable
Architectures. In Jan Haase, editor, \it Models, Methods, and Tools for Complex
Chip Design. Lecture Notes in Electrical Engineering. Volume 265, 2014, pp
@ -925,7 +925,7 @@ control logic because it is simpler than setting up a commercial flow.
\bigskip
\item Direct link to the source code: \\
\smallskip\hskip1cm\url{https://github.com/cliffordwolf/yosys}
\smallskip\hskip1cm\url{https://github.com/YosysHQ/yosys}
\end{itemize}
\end{frame}