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More deadname stuff

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Claire Xenia Wolf 2021-06-09 12:33:41 +02:00
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manual/APPNOTE_012_Verilog_to_BTOR.tex
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@ -52,7 +52,7 @@
\begin{document}
\title{Yosys Application Note 012: \\ Converting Verilog to BTOR}
\author{Ahmed Irfan and Clifford Wolf \\ April 2015}
\author{Ahmed Irfan and Claire Xenia Wolf \\ April 2015}
\maketitle
\begin{abstract}
@ -410,7 +410,7 @@ verification benchmarks with or without memories from Verilog designs.
\begin{thebibliography}{9}
\bibitem{yosys}
Clifford Wolf. The Yosys Open SYnthesis Suite. \\
Claire Xenia Wolf. The Yosys Open SYnthesis Suite. \\
\url{https://yosyshq.net/yosys/}
\bibitem{boolector}