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More deadname stuff

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Claire Xenia Wolf 2021-06-09 12:33:41 +02:00
parent 0ada13cbe2
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10 changed files with 27 additions and 27 deletions
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manual/APPNOTE_010_Verilog_to_BLIF.tex
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@ -52,7 +52,7 @@
\begin{document}
\title{Yosys Application Note 010: \\ Converting Verilog to BLIF}
\author{Clifford Wolf \\ November 2013}
\author{Claire Xenia Wolf \\ November 2013}
\maketitle
\begin{abstract}
@ -437,12 +437,12 @@ design to fit a certain need without actually touching the RTL code.
\begin{thebibliography}{9}
\bibitem{yosys}
Clifford Wolf. The Yosys Open SYnthesis Suite. \\
Claire Xenia Wolf. The Yosys Open SYnthesis Suite. \\
\url{https://yosyshq.net/yosys/}
\bibitem{bigsim}
yosys-bigsim, a collection of real-world Verilog designs for regression testing purposes. \\
\url{https://github.com/cliffordwolf/yosys-bigsim}
\url{https://github.com/YosysHQ/yosys-bigsim}
\bibitem{navre}
Sebastien Bourdeauducq. Navr\'e AVR clone (8-bit RISC). \\