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simlib: fix $priority

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Emil J. Tywoniak 2026-01-19 18:57:52 +01:00
parent 8192cee0b3
commit a7286ca8f5
2 changed files with 19 additions and 2 deletions
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techlibs/common/techmap.v
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@ -694,6 +694,7 @@ module \$priority (A, Y);
wire [WIDTH-1:0] tmp;
(* force_downto *)
wire [WIDTH-1:0] A_active;
(* force_downto *)
wire [WIDTH-1:0] Y_active;
assign A_active = A ^ ~POLARITY;
assign Y = Y_active ^ ~POLARITY;