mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Fix handling of anyconst/anyseq attrs in VHDL code via Verific

Browse source 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-05-15 19:27:00 +02:00
parent 4b6c0e331d
commit a7281930c5
1 changed files with 6 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

12
frontends/verific/verific.cc
View file

@ -871,22 +871,22 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
const char *allconst_attr = net->GetAttValue("allconst"); const char *allconst_attr = net->GetAttValue("allconst");
const char *allseq_attr = net->GetAttValue("allseq"); const char *allseq_attr = net->GetAttValue("allseq");
if (rand_const_attr != nullptr && !strcmp(rand_const_attr, "1")) if (rand_const_attr != nullptr && (!strcmp(rand_const_attr, "1") || !strcmp(rand_const_attr, "'1'")))
anyconst_nets.insert(net); anyconst_nets.insert(net);
else if (rand_attr != nullptr && !strcmp(rand_attr, "1")) else if (rand_attr != nullptr && (!strcmp(rand_attr, "1") || !strcmp(rand_attr, "'1'")))
anyseq_nets.insert(net); anyseq_nets.insert(net);
else if (anyconst_attr != nullptr && !strcmp(anyconst_attr, "1")) else if (anyconst_attr != nullptr && (!strcmp(anyconst_attr, "1") || !strcmp(anyconst_attr, "'1'")))
anyconst_nets.insert(net); anyconst_nets.insert(net);
else if (anyseq_attr != nullptr && !strcmp(anyseq_attr, "1")) else if (anyseq_attr != nullptr && (!strcmp(anyseq_attr, "1") || !strcmp(anyseq_attr, "'1'")))
anyseq_nets.insert(net); anyseq_nets.insert(net);
else if (allconst_attr != nullptr && !strcmp(allconst_attr, "1")) else if (allconst_attr != nullptr && (!strcmp(allconst_attr, "1") || !strcmp(allconst_attr, "'1'")))
allconst_nets.insert(net); allconst_nets.insert(net);
else if (allseq_attr != nullptr && !strcmp(allseq_attr, "1")) else if (allseq_attr != nullptr && (!strcmp(allseq_attr, "1") || !strcmp(allseq_attr, "'1'")))
allseq_nets.insert(net); allseq_nets.insert(net);
if (net_map.count(net)) { if (net_map.count(net)) {