Merge branch 'YosysHQ:main' into main

tests/arch/ecp5/add_sub.py

@@ -1,20 +0,0 @@
-import os
-from pyosys import libyosys as ys
-
-__dir__ = os.path.dirname(os.path.abspath(__file__))
-add_sub = os.path.join(__dir__, "..", "common", "add_sub.v")
-
-base = ys.Design()
-ys.run_pass(f"read_verilog {add_sub}", base)
-ys.run_pass("hierarchy -top top", base)
-ys.run_pass("proc", base)
-ys.run_pass("equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5", base)
-
-postopt = ys.Design()
-ys.run_pass("design -load postopt", postopt)
-ys.run_pass("cd top", postopt)
-ys.run_pass("select -assert-min 25 t:LUT4", postopt)
-ys.run_pass("select -assert-max 26 t:LUT4", postopt)
-ys.run_pass("select -assert-count 10 t:PFUMX", postopt)
-ys.run_pass("select -assert-count 6 t:L6MUX21", postopt)
-ys.run_pass("select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D", postopt)

tests/pyosys/test_ecp5_addsub.py

@@ -1,7 +1,6 @@
 from pathlib import Path
 from pyosys import libyosys as ys
 
-
 __file_dir__ = Path(__file__).absolute().parent
 add_sub = __file_dir__.parent / "arch" / "common" / "add_sub.v"
 

tests/pyosys/test_sigspec_it.py

@@ -0,0 +1,28 @@
+from pyosys import libyosys as ys
+from pathlib import Path
+
+__file_dir__ = Path(__file__).absolute().parent
+
+def _dump_sigbit(bit):
+    if bit.is_wire():
+        if bit.wire.width == 1:
+            return bit.wire.name.str()
+        else:
+            return f"{bit.wire.name} [{bit.offset}]"
+    else:
+        if bit.data == ys.State.S1:
+            return 1
+        elif bit.data == ys.State.S0:
+            return 0
+        else:
+            assert "unknown constants not supported"
+
+d = ys.Design()
+
+ys.run_pass(f"read_verilog {__file_dir__ / 'spm.cut.v.gz'}", d)
+ys.run_pass(f"hierarchy -top spm", d)
+module = d.module(r"\spm")
+for conn_from, conn_to in module.connections_:
+    for bit_from, bit_to in zip(conn_from, conn_to):
+        print(f"assign {_dump_sigbit(bit_from)} = {_dump_sigbit(bit_to)};")
+

tests/sdc/alu_sub.sdc

@@ -0,0 +1,70 @@
+###############################################################################
+# Created by write_sdc
+# Fri Oct  3 11:26:00 2025
+###############################################################################
+current_design wrapper
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name this_clk -period 1.0000 [get_ports {clk}]
+create_clock -name that_clk -period 2.0000 
+create_clock -name another_clk -period 2.0000 \
+    [list [get_ports {A[0]}]\
+          [get_ports {A[1]}]\
+          [get_ports {A[2]}]\
+          [get_ports {A[3]}]\
+          [get_ports {A[4]}]\
+          [get_ports {A[5]}]\
+          [get_ports {A[6]}]\
+          [get_ports {A[7]}]\
+          [get_ports {B[0]}]\
+          [get_ports {B[1]}]\
+          [get_ports {B[2]}]\
+          [get_ports {B[3]}]\
+          [get_ports {B[4]}]\
+          [get_ports {B[5]}]\
+          [get_ports {B[6]}]\
+          [get_ports {B[7]}]]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[0]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[0]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[1]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[1]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[2]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[2]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[3]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[3]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[4]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[4]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[5]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[5]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[6]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[6]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[7]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[7]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[0]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[0]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[1]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[1]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[2]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[2]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[3]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[3]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[4]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[4]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[5]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[5]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[6]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[6]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[7]}]
+set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[7]}]
+group_path -name operation_group\
+    -through [list [get_nets {alu/operation[0]}]\
+           [get_nets {alu/operation[1]}]\
+           [get_nets {alu/operation[2]}]\
+           [get_nets {alu/operation[3]}]]
+###############################################################################
+# Environment
+###############################################################################
+###############################################################################
+# Design Rules
+###############################################################################

tests/sdc/alu_sub.v

@@ -0,0 +1,62 @@
+module adder(
+    input [7:0] a, input [7:0] b, output [7:0] y
+);
+    assign y = a + b;
+endmodule
+
+module wrapper(
+	input clk,
+	input [7:0] A,
+	input [7:0] B,
+	input [3:0] op,
+	output reg [7:0] result
+);
+	wire CF, ZF, SF;
+	alu alu(
+		.clk(clk),
+		.A(A),
+		.B(B),
+		.operation(op),
+		.result(result),
+		.CF(CF),
+		.ZF(ZF),
+		.SF(SF)
+	);
+endmodule
+
+module alu(
+	input clk,
+	input [7:0] A,
+	input [7:0] B,
+	input [3:0] operation,
+	output reg [7:0] result,
+	output reg CF,
+	output reg ZF,
+	output reg SF
+);
+
+	localparam ALU_OP_ADD /* verilator public_flat */ = 4'b0000;
+	localparam ALU_OP_SUB /* verilator public_flat */ = 4'b0001;
+
+	reg [8:0] tmp;
+	reg [7:0] added;
+
+	adder adder(.a(A), .b(B), .y(added));
+
+	always @(posedge clk)
+	begin
+		case (operation)
+			ALU_OP_ADD :
+				tmp = added;
+			ALU_OP_SUB :
+				tmp = A - B;
+		endcase
+
+		CF <= tmp[8];
+		ZF <= tmp[7:0] == 0;
+		SF <= tmp[7];
+
+		result <= tmp[7:0];
+	end
+endmodule
+

tests/sdc/alu_sub.ys

@@ -0,0 +1,14 @@
+read_verilog alu_sub.v
+proc
+hierarchy -auto-top
+
+select -assert-mod-count 1 adder
+select -assert-mod-count 1 wrapper
+select -assert-mod-count 1 alu
+
+sdc -keep_hierarchy alu_sub.sdc
+flatten
+
+select -assert-mod-count 0 adder
+select -assert-mod-count 1 wrapper
+select -assert-mod-count 1 alu

tests/sdc/get_foo.sdc

@@ -0,0 +1 @@
+get_foo -bar 1

tests/sdc/run-test.sh

@@ -0,0 +1,4 @@
+#!/usr/bin/env bash
+set -eu
+source ../gen-tests-makefile.sh
+generate_mk --yosys-scripts --bash

tests/sdc/side-effects.sdc

@@ -0,0 +1,2 @@
+puts "This should print something:"
+puts [get_ports {A[0]}]

tests/sdc/side-effects.sh

@@ -0,0 +1,4 @@
+#!/usr/bin/env bash
+
+../../yosys -p 'read_verilog alu_sub.v; proc; hierarchy -auto-top; sdc side-effects.sdc' | grep 'This should print something:
+YOSYS_SDC_MAGIC_NODE_0'

tests/sdc/unknown-getter.sh

@@ -0,0 +1,5 @@
+#!/usr/bin/env bash
+
+set -euo pipefail
+
+! ../../yosys -p 'read_verilog alu_sub.v; proc; hierarchy -auto-top; sdc get_foo.sdc' 2>&1 | grep 'Unknown getter'