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abc9: respect (* keep *) on cells

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This commit is contained in:
Eddie Hung 2020-01-13 19:21:11 -08:00
parent 9ec948f396
commit a6d4ea7463
3 changed files with 87 additions and 62 deletions
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15
tests/techmap/abc9.ys
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@ -51,3 +51,18 @@ simplemap
equiv_opt -assert abc9 -lut 4
design -load postopt
select -assert-count 2 t:$lut
design -reset
read_verilog -icells <<EOT
module top(input a, b, output o);
wire w;
(* keep *) $_AND_ gate (.Y(w), .A(a), .B(b));
assign o = ~w;
endmodule
EOT
simplemap
equiv_opt -assert abc9 -lut 4
design -load postopt
select -assert-count 1 t:$lut
select -assert-count 1 t:$_AND_