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https://github.com/YosysHQ/yosys
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Added Yosys::{dict,nodict,vector} container types
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parent
e8c12e5f0c
commit
a6c96b986b
21 changed files with 495 additions and 331 deletions
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@ -341,7 +341,7 @@ struct TechmapWorker
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{
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RTLIL::IdString derived_name = tpl_name;
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RTLIL::Module *tpl = map->modules_[tpl_name];
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std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters;
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std::map<RTLIL::IdString, RTLIL::Const> parameters(cell->parameters.begin(), cell->parameters.end());
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if (tpl->get_bool_attribute("\\blackbox"))
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continue;
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@ -529,7 +529,7 @@ struct TechmapWorker
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tpl = techmap_cache[key];
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} else {
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if (cell->parameters.size() != 0) {
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derived_name = tpl->derive(map, parameters);
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derived_name = tpl->derive(map, dict<RTLIL::IdString, RTLIL::Const>(parameters.begin(), parameters.end()));
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tpl = map->module(derived_name);
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log_continue = true;
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}
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@ -975,7 +975,7 @@ struct TechmapPass : public Pass {
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Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend);
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}
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std::map<RTLIL::IdString, RTLIL::Module*> modules_new;
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dict<RTLIL::IdString, RTLIL::Module*> modules_new;
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for (auto &it : map->modules_) {
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if (it.first.substr(0, 2) == "\\$")
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it.second->name = it.first.substr(1);
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@ -1072,7 +1072,7 @@ struct FlattenPass : public Pass {
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log("No more expansions possible.\n");
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if (top_mod != NULL) {
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std::map<RTLIL::IdString, RTLIL::Module*> new_modules;
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dict<RTLIL::IdString, RTLIL::Module*> new_modules;
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for (auto mod : design->modules())
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if (mod == top_mod || mod->get_bool_attribute("\\blackbox")) {
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new_modules[mod->name] = mod;
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