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Added Yosys::{dict,nodict,vector} container types

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This commit is contained in:
Clifford Wolf 2014-12-26 10:53:21 +01:00
parent e8c12e5f0c
commit a6c96b986b
21 changed files with 495 additions and 331 deletions
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2
passes/opt/opt_clean.cc
View file

@ -262,7 +262,7 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
}
std::set<RTLIL::Wire*> del_wires;
nodict<RTLIL::Wire*> del_wires;
int del_wires_count = 0;
for (auto wire : maybe_del_wires)

6
passes/opt/opt_const.cc
View file

@ -196,11 +196,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
ct_combinational.setup_stdcells();
SigMap assign_map(module);
std::map<RTLIL::SigSpec, RTLIL::SigSpec> invert_map;
dict<RTLIL::SigSpec, RTLIL::SigSpec> invert_map;
TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
dict<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
dict<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
for (auto cell : module->cells())
if (design->selected(module, cell) && cell->type[0] == '$') {

18
passes/opt/opt_share.cc
View file

@ -41,7 +41,7 @@ struct OptShareWorker
CellTypes ct;
int total_count;
#ifdef USE_CELL_HASH_CACHE
std::map<const RTLIL::Cell*, std::string> cell_hash_cache;
dict<const RTLIL::Cell*, std::string> cell_hash_cache;
#endif
#ifdef USE_CELL_HASH_CACHE
@ -67,8 +67,8 @@ struct OptShareWorker
for (auto &it : cell->parameters)
hash_string += "P " + it.first.str() + "=" + it.second.as_string() + "\n";
const std::map<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
std::map<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || cell->type == "$add" || cell->type == "$mul" ||
cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") {
@ -127,12 +127,14 @@ struct OptShareWorker
#endif
if (cell1->parameters != cell2->parameters) {
lt = cell1->parameters < cell2->parameters;
std::map<RTLIL::IdString, RTLIL::Const> p1(cell1->parameters.begin(), cell1->parameters.end());
std::map<RTLIL::IdString, RTLIL::Const> p2(cell2->parameters.begin(), cell2->parameters.end());
lt = p1 < p2;
return true;
}
std::map<RTLIL::IdString, RTLIL::SigSpec> conn1 = cell1->connections();
std::map<RTLIL::IdString, RTLIL::SigSpec> conn2 = cell2->connections();
dict<RTLIL::IdString, RTLIL::SigSpec> conn1 = cell1->connections();
dict<RTLIL::IdString, RTLIL::SigSpec> conn2 = cell2->connections();
for (auto &it : conn1) {
if (ct.cell_output(cell1->type, it.first))
@ -171,7 +173,9 @@ struct OptShareWorker
}
if (conn1 != conn2) {
lt = conn1 < conn2;
std::map<RTLIL::IdString, RTLIL::SigSpec> c1(conn1.begin(), conn1.end());
std::map<RTLIL::IdString, RTLIL::SigSpec> c2(conn2.begin(), conn2.end());
lt = c1 < c2;
return true;
}

4
passes/opt/wreduce.cc
View file

@ -28,11 +28,11 @@ PRIVATE_NAMESPACE_BEGIN
struct WreduceConfig
{
std::set<IdString> supported_cell_types;
nodict<IdString> supported_cell_types;
WreduceConfig()
{
supported_cell_types = std::set<IdString>({
supported_cell_types = nodict<IdString>({
"$not", "$pos", "$neg",
"$and", "$or", "$xor", "$xnor",
"$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",