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Added Yosys::{dict,nodict,vector} container types

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This commit is contained in:
Clifford Wolf 2014-12-26 10:53:21 +01:00
parent e8c12e5f0c
commit a6c96b986b
21 changed files with 495 additions and 331 deletions
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8
passes/cmds/rename.cc
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@ -118,7 +118,7 @@ struct RenamePass : public Pass {
if (!design->selected(module))
continue;
std::map<RTLIL::IdString, RTLIL::Wire*> new_wires;
dict<RTLIL::IdString, RTLIL::Wire*> new_wires;
for (auto &it : module->wires_) {
if (it.first[0] == '$' && design->selected(module, it.second))
do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
@ -128,7 +128,7 @@ struct RenamePass : public Pass {
module->wires_.swap(new_wires);
module->fixup_ports();
std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
for (auto &it : module->cells_) {
if (it.first[0] == '$' && design->selected(module, it.second))
do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
@ -149,7 +149,7 @@ struct RenamePass : public Pass {
if (!design->selected(module))
continue;
std::map<RTLIL::IdString, RTLIL::Wire*> new_wires;
dict<RTLIL::IdString, RTLIL::Wire*> new_wires;
for (auto &it : module->wires_) {
if (design->selected(module, it.second))
if (it.first[0] == '\\' && it.second->port_id == 0)
@ -159,7 +159,7 @@ struct RenamePass : public Pass {
module->wires_.swap(new_wires);
module->fixup_ports();
std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
for (auto &it : module->cells_) {
if (design->selected(module, it.second))
if (it.first[0] == '\\')