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Added Yosys::{dict,nodict,vector} container types

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This commit is contained in:
Clifford Wolf 2014-12-26 10:53:21 +01:00
parent e8c12e5f0c
commit a6c96b986b
21 changed files with 495 additions and 331 deletions
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8
passes/cmds/delete.cc
View file

@ -91,10 +91,10 @@ struct DeletePass : public Pass {
continue;
}
std::set<RTLIL::Wire*> delete_wires;
std::set<RTLIL::Cell*> delete_cells;
std::set<RTLIL::IdString> delete_procs;
std::set<RTLIL::IdString> delete_mems;
nodict<RTLIL::Wire*> delete_wires;
nodict<RTLIL::Cell*> delete_cells;
nodict<RTLIL::IdString> delete_procs;
nodict<RTLIL::IdString> delete_mems;
for (auto &it : module->wires_)
if (design->selected(module, it.second))

8
passes/cmds/rename.cc
View file

@ -118,7 +118,7 @@ struct RenamePass : public Pass {
if (!design->selected(module))
continue;
std::map<RTLIL::IdString, RTLIL::Wire*> new_wires;
dict<RTLIL::IdString, RTLIL::Wire*> new_wires;
for (auto &it : module->wires_) {
if (it.first[0] == '$' && design->selected(module, it.second))
do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
@ -128,7 +128,7 @@ struct RenamePass : public Pass {
module->wires_.swap(new_wires);
module->fixup_ports();
std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
for (auto &it : module->cells_) {
if (it.first[0] == '$' && design->selected(module, it.second))
do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
@ -149,7 +149,7 @@ struct RenamePass : public Pass {
if (!design->selected(module))
continue;
std::map<RTLIL::IdString, RTLIL::Wire*> new_wires;
dict<RTLIL::IdString, RTLIL::Wire*> new_wires;
for (auto &it : module->wires_) {
if (design->selected(module, it.second))
if (it.first[0] == '\\' && it.second->port_id == 0)
@ -159,7 +159,7 @@ struct RenamePass : public Pass {
module->wires_.swap(new_wires);
module->fixup_ports();
std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
for (auto &it : module->cells_) {
if (design->selected(module, it.second))
if (it.first[0] == '\\')

4
passes/cmds/select.cc
View file

@ -101,7 +101,7 @@ static bool match_attr_val(const RTLIL::Const &value, std::string pattern, char
log_abort();
}
static bool match_attr(const std::map<RTLIL::IdString, RTLIL::Const> &attributes, std::string name_pat, std::string value_pat, char match_op)
static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, std::string name_pat, std::string value_pat, char match_op)
{
if (name_pat.find('*') != std::string::npos || name_pat.find('?') != std::string::npos || name_pat.find('[') != std::string::npos) {
for (auto &it : attributes) {
@ -119,7 +119,7 @@ static bool match_attr(const std::map<RTLIL::IdString, RTLIL::Const> &attributes
return false;
}
static bool match_attr(const std::map<RTLIL::IdString, RTLIL::Const> &attributes, std::string match_expr)
static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, std::string match_expr)
{
size_t pos = match_expr.find_first_of("<!=>");

2
passes/cmds/setattr.cc
View file

@ -50,7 +50,7 @@ struct setunset_t
}
};
static void do_setunset(std::map<RTLIL::IdString, RTLIL::Const> &attrs, std::vector<setunset_t> &list)
static void do_setunset(dict<RTLIL::IdString, RTLIL::Const> &attrs, std::vector<setunset_t> &list)
{
for (auto &item : list)
if (item.unset)

2
passes/cmds/splitnets.cc
View file

@ -176,7 +176,7 @@ struct SplitnetsPass : public Pass {
module->rewrite_sigspecs(worker);
std::set<RTLIL::Wire*> delete_wires;
nodict<RTLIL::Wire*> delete_wires;
for (auto &it : worker.splitmap)
delete_wires.insert(it.first);
module->remove(delete_wires);