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https://github.com/YosysHQ/yosys
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Use edges when explicit
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cbadfa0268
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@ -74,6 +74,7 @@ struct SimShared
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double start_time = 0;
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double start_time = 0;
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double stop_time = -1;
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double stop_time = -1;
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SimulationMode sim_mode = SimulationMode::cmp;
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SimulationMode sim_mode = SimulationMode::cmp;
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bool cycles_set = false;
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};
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};
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void zinit(State &v)
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void zinit(State &v)
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@ -1016,7 +1017,9 @@ struct SimWorker : SimShared
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log_error("Stop time is before start time\n");
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log_error("Stop time is before start time\n");
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}
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}
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auto edges = fst->getAllEdges(fst_clock, startCount, stopCount);
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auto edges = fst->getAllEdges(fst_clock, startCount, stopCount);
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if (cycles_set && ((size_t)(numcycles *2) < edges.size()))
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edges.erase(edges.begin() + (numcycles*2), edges.end());
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if ((startCount == stopCount) && writeback) {
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if ((startCount == stopCount) && writeback) {
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log("Update initial state with values from %zu\n",startCount);
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log("Update initial state with values from %zu\n",startCount);
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if (edges.empty())
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if (edges.empty())
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@ -1143,6 +1146,7 @@ struct SimPass : public Pass {
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}
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}
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if (args[argidx] == "-n" && argidx+1 < args.size()) {
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if (args[argidx] == "-n" && argidx+1 < args.size()) {
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numcycles = atoi(args[++argidx].c_str());
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numcycles = atoi(args[++argidx].c_str());
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worker.cycles_set = true;
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continue;
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continue;
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}
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}
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if (args[argidx] == "-rstlen" && argidx+1 < args.size()) {
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if (args[argidx] == "-rstlen" && argidx+1 < args.size()) {
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