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https://github.com/YosysHQ/yosys
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patch: don't track root cell deletions for perf
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parent
e2a77db87a
commit
a689cdc6ed
2 changed files with 8 additions and 3 deletions
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@ -88,7 +88,7 @@ struct SrcCollector {
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}
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};
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void Patch::gc(Cell* old_cell) {
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void Patch::gc(Cell* old_cell, bool track) {
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log_debug("gc %s\n", old_cell->name);
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if (old_cell->type.in(ID($input_port), ID($output_port), ID($public)))
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return;
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@ -119,9 +119,13 @@ void Patch::gc(Cell* old_cell) {
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}
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}
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log_debug("\tremove %s\n", old_cell->name);
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// Only track recursively-removed cells. The top-level patched cell is the
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// caller's current iteration variable and won't be re-encountered.
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if (track && removed_cells)
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removed_cells->insert(old_cell);
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old_cell->module->remove(old_cell);
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for (auto input : inputs)
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gc(input);
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gc(input, /*track=*/true);
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}
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Wire* Patch::commit_wire(std::unique_ptr<Wire> wire) {
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@ -10,7 +10,7 @@ YOSYS_NAMESPACE_BEGIN
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struct RTLIL::Patch : public CellAdderMixin<RTLIL::Patch>
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{
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private:
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void gc(Cell* old_cell);
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void gc(Cell* old_cell, bool track = false);
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protected:
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void add(RTLIL::Wire *wire);
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@ -25,6 +25,7 @@ protected:
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public:
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Module* mod;
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SigMap* map;
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pool<Cell*>* removed_cells = nullptr;
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vector<std::unique_ptr<Wire>> wires_ = {};
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vector<std::unique_ptr<Cell>> cells_ = {};
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