Remove trailing whitespaces

tests/sim/generate_mk.py

@@ -11,7 +11,7 @@ from pathlib import Path
 print("Generate FST for sim models")
 
 for name in Path("tb").rglob("tb*.v"):
-    test_name = name.stem 
+    test_name = name.stem
     print(f"Test {test_name}")
 
     verilog_name = f"{test_name[3:]}.v"

tests/sim/tb/tb_adff.v

@@ -1,4 +1,4 @@
-`timescale 1ns/1ns 
+`timescale 1ns/1ns
 module tb_adff();
 	reg clk = 0;
 	reg rst = 0;

tests/sim/tb/tb_adffe.v

@@ -1,4 +1,4 @@
-`timescale 1ns/1ns 
+`timescale 1ns/1ns
 module tb_adffe();
 	reg clk = 0;
 	reg rst = 0;

tests/sim/tb/tb_adlatch.v

@@ -1,4 +1,4 @@
-`timescale 1ns/1ns 
+`timescale 1ns/1ns
 module tb_adlatch();
 	reg clk = 0;
 	reg rst = 0;

tests/sim/tb/tb_aldff.v

@@ -1,4 +1,4 @@
-`timescale 1ns/1ns 
+`timescale 1ns/1ns
 module tb_aldff();
 	reg clk = 0;
 	reg aload = 0;

tests/sim/tb/tb_aldffe.v

@@ -1,4 +1,4 @@
-`timescale 1ns/1ns 
+`timescale 1ns/1ns
 module tb_aldffe();
 	reg clk = 0;
 	reg aload = 0;

tests/sim/tb/tb_dff.v

@@ -1,4 +1,4 @@
-`timescale 1ns/1ns 
+`timescale 1ns/1ns
 module tb_dff();
 	reg clk = 0;
 	reg d = 0;

tests/sim/tb/tb_dffe.v

@@ -1,4 +1,4 @@
-`timescale 1ns/1ns 
+`timescale 1ns/1ns
 module tb_dffe();
 	reg clk = 0;
 	reg en = 0;

tests/sim/tb/tb_dffsr.v

@@ -1,4 +1,4 @@
-`timescale 1ns/1ns 
+`timescale 1ns/1ns
 module tb_dffsr();
 	reg clk = 0;
 	reg d = 0;

tests/sim/tb/tb_dlatch.v

@@ -1,4 +1,4 @@
-`timescale 1ns/1ns 
+`timescale 1ns/1ns
 module tb_dlatch();
 	reg clk = 0;
 	reg en = 0;

tests/sim/tb/tb_dlatchsr.v

@@ -1,4 +1,4 @@
-`timescale 1ns/1ns 
+`timescale 1ns/1ns
 module tb_dlatchsr();
 	reg d = 0;
 	reg set = 0;

tests/sim/tb/tb_sdff.v

@@ -1,4 +1,4 @@
-`timescale 1ns/1ns 
+`timescale 1ns/1ns
 module tb_sdff();
 	reg clk = 0;
 	reg rst = 0;

tests/sim/tb/tb_sdffce.v

@@ -1,4 +1,4 @@
-`timescale 1ns/1ns 
+`timescale 1ns/1ns
 module tb_sdffce();
 	reg clk = 0;
 	reg rst = 0;

tests/sim/tb/tb_sdffe.v

@@ -1,4 +1,4 @@
-`timescale 1ns/1ns 
+`timescale 1ns/1ns
 module tb_sdffe();
 	reg clk = 0;
 	reg rst = 0;