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Remove trailing whitespaces

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This commit is contained in:
Miodrag Milanovic 2026-06-23 07:24:59 +02:00
parent 48a3dcc02a
commit a689342207
317 changed files with 3136 additions and 3136 deletions
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4
tests/asicworld/code_verilog_tutorial_comment.v
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@ -15,11 +15,11 @@ input ci;
// Output ports
output sum;
output co;
// Data Types
// Data Types
wire a;
wire b;
wire ci;
wire sum;
wire co;
wire co;
endmodule